GL424 datasheet(6/34 Pages) GENESYS

6 / 34 page

GL424 SD/MMC Flash Card Controller

Page 6

LIST OF TABLES

TABLE 3.1 - 46 PIN LQFN REGULATOR INTERFACE ....................................................... 16

TABLE 3.2 - 54 PIN VFBGA REGULATOR INTERFACE .................................................... 16

TABLE 3.3 – DIE PAD REGULATOR INTERFACE................................................................ 16

TABLE 3.4 – 46 PIN LGA REGULATOR INTERFACE......................................................... 17

TABLE 3.5 – 51 PIN LGA REGULATOR INTERFACE......................................................... 17

TABLE 3.3 - 46 PIN LQFN CARD INTERFACE .................................................................. 18

TABLE 3.4 - 54 PIN VFBGA CARD INTERFACE ............................................................... 18

TABLE 3.5 – DIE PAD CARD INTERFACE ........................................................................... 19

TABLE 3.6 - 46 PIN LGA CARD INTERFACE..................................................................... 20

TABLE 3.7 - 51 PIN LGA CARD INTERFACE..................................................................... 20

TABLE 3.8 - 46 PIN LQFN FLASH INTERFACE ................................................................. 21

TABLE 3.9 - 54 PIN VFBGA FLASH INTERFACE .............................................................. 21

TABLE 3.10 – DIE PAD FLASH INTERFACE........................................................................ 22

TABLE 3.11 – 46 PIN LGA FLASH INTERFACE................................................................. 23

TABLE 3.12 – 51 PIN LGA FLASH INTERFACE................................................................. 23

TABLE 3.13 - 46 PIN LQFN SYSTEM INTERFACE ............................................................ 24

TABLE 3.14 - 54 PIN VFBGA SYSTEM INTERFACE.......................................................... 24

TABLE 3.15 - DIE PAD SYSTEM INTERFACE ...................................................................... 25

TABLE 3.16 - 46 PIN LGA SYSTEM INTERFACE ............................................................... 26

TABLE 3.17 - 51 PIN LGA SYSTEM INTERFACE ............................................................... 26

TABLE 3.18 - 54 PIN VFBGA TEST INTERFACE .............................................................. 27

TABLE 3.19 - DIE PAD TEST INTERFACE........................................................................... 27

TABLE 4.1 - ABSOLUTE MAXIMUM RATINGS.................................................................... 28

TABLE 4.2 - BUS OPERATING CONDITIONS ....................................................................... 28

TABLE 4.3 - D.C. CHARACTERISTICS ................................................................................ 28

TABLE 6.1- ORDERING INFORMATION .............................................................................. 34

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