TDA7421N

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3.2.4 INLOCK DETECTOR

The charge pump is switched in low current mode as the truth table and the related figure shows.

The charge pump is forced in low current mode when a phase difference of 10-40 usec is reached.

A phase difference larger than the programmed values will switch the charge pump immediately in the high cur-

rent mode.

Few programmable delays are available for inlock detection.

4.0 IF COUNTER SYSTEM FOR AM/FM

The IF counter mode is controlled by IFCM register:

A sample timer to generate the gate signal for the main counter is built with a 14 bit programmable counter to

have the possibility to use any frequency. In FM mode a 6.25 KHz, in AM mode a 1KHz signal is generated.

This counter is followed by an asynchronous divider to generate several sampling times.

ADDRESS ORGANIZATION (PLL and IF Counter)

CURRHIGH

LOCKENA

LOCK (by inlock detector)

Charge PumpCurrent

0

X

X

low current

1

1

1

low current

1

1

0

High current

1

0

1

High current

1

0

0

High current

IFCM1

IFCM0

FUNCTION

0

0

NOT USED

0

1

FM MODE

1

0

AM MODE

1

1

NOT USED

MSB

LSB

FUNCTION

SUBAD

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

PLL CHARGE PUMP

00H

LPIN1/2 CURRH

B1

B0

A3

A2

A1

A0

LL COUNTER

01H

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PLL COUNTER

02H

PC15

PC14

PC13

PC12

PC11

PC10

PC9

PC8

LL REF COUNTER

03H

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

LL REF COUNTER

04H

RC15

RC14

RC13

RC12

RC11

RC10

RC9

RC8

LL LOCK DETECT

05H

LDENA

-

D3

D2

D1

D0

PM1

PM0

FC REF COUNTER

06H

IRC7

IRC6

IRC5

IRC4

IRC3

IRC2

IRC1

IRC0

FC REF COUNTER

07H

IFCM1

IFCM0

IRC13

IRC12

IRC11

IRC10

IRC9

IRC8

FC CONTROL

08H

IFENA

----

EW2

EW1

EW0

C CONTROL

09H

IFS2

IFS1

IFS0

CF4

CF3

CF2

CF1

CF0