TDA7421N

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ttim = (IFRC + 1) / fosc

tcnt = (CF + 1697) / fIF FM mode

tcnt = (CF + 44) / fIF AM mode

Counter result succeeded:

ttim > tcnt - terr and

ttim > tcnt + terr

Counter result failed:

ttim< tcnt + terr or

ttim > tcnt - terr

where:

ttim = IF time cycle time

tcnt = IF counter cycle time

terr = discrimination window (controlled by the EW registers)

The precision of the measurements is adjustable by controlling the discrimination window. This is adjustable by

programming the control registers EW0...EW2.

The measurement time per cycle is adjustable by setting the register IFS0 - IFS2.

The center frequency of the discrimination window is adjustable by the control register "CF0" to "CF4". The avail-

able values are reported in databyte specification

5.0 I

5.1 General Description

The TDA7421N supports the I2C bus protocol. This protocol defines the devices sending data into the bus as

transmitter and the receiving device as the receiver.

The device that controls the transfer is a master and the device being controlled is the slave. The master will

always initiates data transfer and provide the clock to transmit or receive operations.

5.2 Data Transition

Data transition on the SDA line must only occur when the clock SCL is low. SDA transitions while SCL is high

will be interpreted as START or STOP condition.

5.3 Start Condition

A start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a stable HIGH level.

This START condition must precede any command and initiate a data transfer onto the bus.The TDA7421N con-

tinuously monitors the SDA and SCL lines for a valid START and will not response to any command if this con-

dition has not been met.

5.4 Stop condition

A STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at a stable HIGH

level. This condition terminate the communication between the devices and force's the bus interface of the

TDA7421N into the initial condition.

succeeded

failed

failed

D96AU551