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HF88S05

SRAM Series

December 18, 2003

5

V1.00

This specification is subject to change without notice. Please contact sales person for the latest version before use.

5. Function Block Diagram

Several registers are used in the interface logic. The functions of the registers are described below and

their initial values are as indicated in the following table.

TPP

TPL

TP[15..0]

TPH

XOR

Static

DIN[7..0]

S2P

MUX

+ 1

DOUT[7..0]

CHKSUM

RAM

MUX

ARRAY

64Kx8

MUX

The Table Pointer register keeps the address of SRAM being written to or read from.

It will

automatically increment by one with each read/write access, but remains unchanged when writing

command or reading checksum.

The Checksum Register keeps the Exclusive OR checksum of the data bytes as they are written to/read

from SRAM. The Checksum register cannot be written but it is cleared by any access to the TPL, TPH

Register

Type

Description

Initial Value

TPL

W

Address register 0 for A7 ~ A0

“--------“

TPH

W

Address register 1 for A15 ~ A8

“--------“

TPP

W

Address register 2 for A23 ~ A16

“--------“

Checksum

R

XOR checksum of data

“--------“