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HF88S05

SRAM Series

December 18, 2003

3

V1.00

This specification is subject to change without notice. Please contact sales person for the latest version before use.

3. Pin Description

HF88S05

13

11

10

18

5

15

16

12

9

8

7

6

1

4

14

17

3

2

D7

D5

D4

VDD

R_WN

SDI

SDO

D6

D3

D2

D1

D0

P_SN

D_CN

SCLK

CS1

CS0N

VSS

Symbol I/O Description

P_Sn

I

Input to select either parallel (when ‘1’) or serial (when ‘0’) interface is used for transferring data.

VSS

I

Negative power supply of the device

CS0n

I

CS0n is active low chip select input pin. The device is selected when CS1 is high and CS0n is

low simultaneously. Otherwise, it is deselected.

D_Cn

I

Input to select either the SRAM or Registers (TPP, TPH, TPL, Mode or Checksum) operations.

R_Wn

I

Input to select either a Read operation (when ‘1’) or a write operation (when ‘0’) is to be

performed.

D0 ~ D7

I/O Bi-directional data bus for parallel transfer mode.

SCLK/

Strobe

I

This pin is shared between parallel and serial modes. In serial mode, this pin is Serial Clock

SCLK for transferring the data from/to SDI/SDO. In parallel mode, it is the strobe signal used to

write the registers and SRAM as well as read the checksum and contents of SRAM. This pin is

equipped with Schmidt type input structure to prevent the input from chattering due to slow rising

clock source transition.

SDI

I

Serial Data Input for writing to either Registers or SRAM.

SDO

O Serial Data Output for reading data from either Checksum Register or SRAM.

CS1

I

CS1 is active high chip select input. The device is selected when CS1 is high and CS0n is low

simultaneously. Otherwise, it is deselected.

VDD

I

Positive power supply of the device