KING BILLION ELECTRONICS CO., LTD

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HF88S05

SRAM Series

December 18, 2003

6

V1.00

This specification is subject to change without notice. Please contact sales person for the latest version before use.

and TPP registers.

6. Parallel Mode

When in parallel mode, an 8-bit data bus D[7..0] are used to transfer information between MCU and

SRAM. The advantage of parallel transfer mode is that higher speed can be achieved. To operate in

parallel mode, the P_Sn pin should be driven with high level voltage.

6.1. Parallel Write Command Mode

Loading of Addresses and Mode Register in parallel mode are by asserting the Strobe (going low and then

high) in write command mode (both R_Wn and D_Cn are low), which will also clear the CHKSUM

register at the same time. After the previous data transfer or when the device is just selected (CS1 is

high and CS0n is low), the command data will be written to registers in the order of TPL, TPH, TPP, then

Mode, TPL… So when unsure, a dummy data read or deselect and select the device again will reset the

register select.

The timing chart below exemplifies when original TP is unknown, then 0x00, 0x01, 0x02 addresses were

written sequentially to TPL, TPH, and then TPP, the TP becomes 0x020100h.

CS0_n

CS1

P_Sn

D_Cn

R_Wn

D[7:0]

SCLK

TP

(TPP, TPH, TPL)

00

01

02

xxxxxx

xxxx00

xx0100

020100

55

Parallel Command/Data Write Mode

TPL

TPH

TPP

T

Setup

T

Hold

020101

020102

aa

78

020103

T

Ass

6.2. Parallel Write Data Mode

To write data to SRAM in parallel mode, assert Strobe in Data Write Mode (D_Cn @ Vih and R_Wn at

Vil). The checksum register will be updated, and the TP register will be incremented at the rising edge of

Strobe signal.