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HF88S05

SRAM Series

December 18, 2003

10

V1.00

This specification is subject to change without notice. Please contact sales person for the latest version before use.

CS0_n

CS1

P_Sn

D_Cn

R_Wn

SDO

SCLK

TP

(TPP, TPH, TPL)

b7

020100

Series Data Read Mode

SDI

b1

b0

b7

b6

b6

b5

b4

b3

b2

b5

b7

b6

b4

b3

b2

b1

b0

020102

The bit 7 shall be shifted into register first

020101

User shall update the initial address (TP) before

reading the data from SRAM.

User shall dummy read 8 bits, and then the real

first msb b7 will be output.

Internal Strobe signal is used to latch SRAM data into shifter register, and generated at each 8th sclk.

Internal

Strobe

7.5. Serial Command Read Mode

Reading checksum in serial mode is similar to Read data mode except that the D_Cn is at low level

instead of high.

8. Power consideration

In order to conserve power consumed by the device, the static power consumption by SRAM sense

amplifier need to be minimized. Since the sense amplifier is on whenever the device is selected and

Strobe/SCLK is asserted low in Data Read Mode. Therefore the way to save power is to minimize the

duty of the overall Strobe/SCLK signal to an extent that it is just long enough to satisfy the access time so

that the static power consumption can be lower.