KING BILLION ELECTRONICS CO., LTD

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HF88S05

SRAM Series

December 18, 2003

7

V1.00

This specification is subject to change without notice. Please contact sales person for the latest version before use.

6.3. Parallel Read Data Mode

To Read from SRAM in parallel mode, assert the Strobe in Read Data mode (R_Wn at high and D_Cn

low). The data will appear on the Data bus after proper access time. The TP will increment and

Checksum will update at the rising edge of Strobe. Register select will be reset by Read Data operation.

CS0_n

CS1

P_Sn

D_Cn

R_Wn

D[7:0]

SCLK

TP

(TPP, TPH, TPL)

00

01

02

xxxxxx

xxxx00

xx0100

020100

55

Parallel Data/Checksum Read Mode

TPL

TPH

TPP

T

Setup

T

Hold

020101

020102

020103

aa

78

Checksum

3F

T

RD

T

Ass

T

CG

6.4. Parallel Checksum Read Mode

To read the checksum result from previous data transfer (either from SRAM or to SRAM), assert the

Strobe signal in Read Command mode (R_Wn is high and D_Cn low).

7. Serial Mode

The serial interface is preferable to parallel interface in applications where I/O pins are limited. The

interface logic circuit is basically the same as the parallel mode except that an internal shift register and

bit counter are used to facilitate transferring serial data from/to external MCU.

Multiple devices array can also be used in serial mode. The chip array is connected in daisy chain

manner. The MCU’s serial data output pin drives the SDI pin of the first device. The SDO pin of the

device then, in turn, drives the SDI pin of the next device in the chain. The SDO pin of the last device

then connects back to the MCU’s SDI pin to complete the loop.

There could be only one active device in the array at one time, while the other device must be deselected.

7.1. Bi-directional Synchronous Serial Data Interface

The Serial interface is a Bi-directional Synchronous Serial Interface. The Serial Data can be written to

Registers (such as TPL, TPH, TPP registers) as well as SRAM through the serial interface. The