LT8418 datasheet(32/50 Pages) AD

32 / 50 page

Data Sheet

LTC7892

analog.com

Rev. 0

32 of 50

If one of the DTCx pins is programmed with a resistor, the other DTCx pin must be programmed with a resistor for

proper dead time control operation. Unexpected dead time delays can result if one DTCx pin is programmed with a

resistor while the other DTCx pin is tied to GND. The DTCx pins should only be connected to GND or a resistor tied to

GND.

Power FET Selection

Two external power FETs must be selected for each controller in the LTC7892: one N-channel FET for the bottom

(main) switch and one N-channel FET for the top (synchronous) switch. The peak-to-peak gate drive levels are set by

the INTVCC regulation point (4V to 5.5V). Most GaN FETs can be driven comfortably within this INTVCC regulation

window. If using silicon MOSFETs, logic-level threshold MOSFETs must be used in most applications. Pay close

attention to the BVDSS specification for the FETs as well.

Selection criteria for the power FETs include the on resistance (RDS(ON)), Miller capacitance (CMILLER), input voltage, and

maximum output current. CMILLER, can be approximated from the gate charge curve typically provided in the

datasheet of the FET manufacturer. CMILLER is equal to the increase in gate charge along the horizontal axis, while the

curve is approximately flat, divided by the specified change in the voltage difference between the drain and source

terminals of the FET (VDS). This result is then multiplied by the ratio of the application applied VDS to the gate charge

curve specified VDS. When the IC is operating in continuous mode, the duty cycles for the top and bottom FETs are

given by Equation 10 and Equation 11, as follows:

Main Switch Duty Cycle =

VOUT − VIN

VOUT

(10)

Synchronous Switch Duty Cycle =

VIN

VOUT

(11)

The FET power dissipation at maximum output current is given by Equation 12 and Equation 13, as follows:

PMAIN =

(VOUT−VIN)VOUT

IN2

(IOUT(MAX))

2• (1 + δ)R

DS(ON) + (

OUT3

VIN

) (

IOUT(MAX)

)

•

(RDR)(CMILLER) • ⌊

VINTVCC−VTHMIN

VTHMIN

⌋ (f)

(12)

PSYNC =

VOUT

VIN

(IOUT(MAX))

(1 + δ)RDS(ON)

(13)

where:

PMAIN is the power dissipation from the main switch

δ is the temperature dependency of RDS(ON) (δ ≈ 0.005/°C).

RDR is the effective driver resistance at the FET’s Miller threshold voltage (RDR ≈ 2Ω).

VINTVCC is the INTVCC voltage.

VTHMIN is the typical FET minimum threshold voltage.

PSYNC is the power dissipation from the synchronous switch.

Both FETs have I2R losses (I2R is the power loss equation of the FETs when on in steady state), whereas the main

N-channel equations include an additional term for transition losses, which are highest at low input voltages. For

high input voltages, the high current efficiency generally improves with larger FETs. However, for low input voltages,

the transition losses rapidly increase to the point that using a higher RDS(ON) device with lower CMILLER provides higher

efficiency. The synchronous FET losses are greatest at high input voltages when the bottom switch duty factor is low.

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