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Data Sheet

LTC7892

analog.com

Rev. 0

39 of 50

Minimum On-Time Considerations

The minimum on-time (tON(MIN)) is the shortest time duration that the LTC7892 is capable of turning on the bottom

FET. TON(MIN) is determined by internal timing delays and the gate charge required to turn on the bottom FET.

Low-duty cycle applications can approach this minimum on-time limit. Ensure the results in Equation 21, as follows:

tON(MIN) <

VOUT − VIN

VOUT • f

(21)

If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC7892 begins to skip cycles.

The output voltage continues to regulate, but the ripple voltage and current will increase. The minimum on-time for

the LTC7892 is approximately 100ns. If VIN increases, thereby further decreasing the duty cycle, more cycles are

skipped, and the LTC7892 can turn on the top FET continuously. If the bottom FET is not turned on frequently enough

to recharge the bootstrap capacitor, the top FET will not fully enhance, or it can be completely off when the LTC7892

turns on the top FET. Thus, the LTC7892 cannot achieve 100% top FET on operation.

Fault Conditions: Overtemperature Protection

At higher temperatures, or in cases where the internal power dissipation causes excessive self-heating (such as a

short from INTVCC to ground), internal overtemperature shutdown circuitry will shut down the LTC7892. When the

internal die temperature exceeds 180°C, the INTVCC LDO regulator and the gate drivers are disabled. When the die

cools to 160°C, the LTC7892 enables the INTVCC LDO regulator and resumes operation, beginning with a soft-start

startup. Avoid long-term overstress (TJ > 125°C) because it can degrade the performance or shorten the life of the

device.

Phase-Locked Loop and Frequency Synchronization

The LTC7892 has an internal PLL that allows the turn-on of the bottom FET of channel 1 to be synchronized to the

rising edge of an external clock signal applied to the PLLIN/SPREAD pin. The turn-on of channel 2 bottom FET is 180°

out of phase with the external clock.

Rapid phase-locking can be achieved by using the FREQ pin to set a free-running frequency near the desired

synchronization frequency. Before synchronization, the PLL is prebiased to the frequency set by the FREQ pin.

Consequently, the PLL only needs to make minor adjustments to achieve phase-lock and synchronization. Although

it is not required, placing the free-running frequency be near the external clock frequency prevents the oscillator

from passing through a large range of frequencies as the PLL locks.

When synchronized to an external clock, the LTC7892 operates in pulse-skipping mode if it is selected by the MODE

pin, or in forced continuous mode otherwise. The LTC7892 is guaranteed to synchronize to an external clock applied

to the PLLIN/SPREAD pin that swings up to at least 2.2V and down to 0.5V or less. Note that the LTC7892 can only be

synchronized to an external clock frequency within the range of 100kHz to 3MHz.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%.

Analyzing individual losses is useful for determining what limits the efficiency and which change would produce the

most improvement. Percent efficiency can be expressed by Equation 22 as follows:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

(22)

where L1, L2, L3, and so on, are the individual losses as a percentage of input power.

Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the

losses in LTC7892 circuits: IC VBIAS current, INTVCC regulator current, I2R losses, and bottom-side FET transition losses.

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