LT8418 datasheet(40/50 Pages) AD

40 / 50 page

Data Sheet

LTC7892

analog.com

Rev. 0

40 of 50

1. The VBIAS current is the DC supply current given in Table 1 (Electrical Characteristics table), which excludes

FET drivers and control currents. Other than at very light loads in Burst Mode operation, VBIAS current typically

results in a small (<0.1%) loss.

2. The INTVCC current is the sum of the FET driver and control currents. The FET driver current results from

switching the gate capacitance of the power FETs. Each time a FET gate is switched from low to high to low

again, a packet of charge (dQ) moves from INTVCC to GND. The resulting dQ/time duration (dt) is a current

out of INTVCC that is typically much larger than the control circuit current. In continuous mode, gate charge

current (IGATECHG) = frequency (f) x (QT + QB), where QT and QB are the gate charges of the top and bottom FETs.

3. I2R losses are predicted from the DC resistances of the input fuse (if used), FET, inductor, current sense

resistor, and input and output capacitor ESR. In continuous mode, the average output current flows through

L and RSENSE, but is chopped between the top and bottom FETs. If the two FETs have approximately the same

RDS(ON), the resistance of one FET can simply be summed with the resistances of L, RSENSE, and ESR to obtain

the I2R losses.

4. Transition losses apply only to the bottom FETs and become significant only when operating at higher

output voltages (typically 20V or greater) or at high frequency (MHz range). Transition losses can be

estimated using Equation 23, as follows:

TRANSITION LOSS = (1.7)

VOUT

VIN

IL(MAX) • CMILLER • f

(23)

where:

IL(MAX) is the maximum average inductor current.

CMILLER is the Miller capacitance.

f is the operating frequency.

Other hidden losses, such as copper trace and internal battery resistances, can account for an additional 5% to 10%

efficiency degradation in portable systems. It is very important to include these system-level losses during the design

phase. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge

storage and very low ESR at the switching frequency. A 25W supply typically requires a minimum of 20μF to 40μF of

capacitance having a maximum of 20mΩ to 50mΩ of ESR. Other losses, including inductor core losses, generally

account for less than 2% of the total additional loss.

Checking Transient Response

To check the regulator loop response, look at the load current transient response. Switching regulators take several

cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUTx shifts by an amount equal to

ΔILOAD • (ESR), where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT,

generating the feedback error signal that forces the regulator to adapt to the current change and return VOUTx to its

steady-state value. During this recovery time VOUTx can be monitored for excessive overshooting or ringing, which

would indicate a stability problem.

OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance

and ESR values. The availability of the ITHx pin not only allows optimization of control loop behavior but also

provides a DC-coupled and AC-filtered closed-loop response test point. The DC step, rise time, and settling at this

test point truly reflect the closed-loop response. Assuming a predominantly second-order system, the phase margin

and/or damping factor can be estimated using the percentage of overshoot seen at the ITHx pin. The bandwidth can

also be estimated by examining the rise time at the ITHx pin. The ITHx external components shown in the Typical

Applications section provide an adequate starting point for most applications.

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