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LT8418 Datasheet(PDF) 23 Page - Analog Devices |
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LT8418 Datasheet(HTML) 23 Page - Analog Devices |
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23 / 50 page ![]() Data Sheet LTC7892 analog.com Rev. 0 23 of 50 edge of the synchronizing signal. The turn-on of the external bottom FET for Channel 2 is 180° out-of-phase to the rising edge of the external clock source. The PLL frequency is prebiased to the free running frequency set by the FREQ pin before the external clock is applied. If prebiased near the external clock frequency, the PLL only needs to make slight changes to synchronize the rising edge of the external clock to the rising edge of BG1. For a more rapid lock-in to the external clock, use the FREQ pin to set the internal oscillator to approximately the frequency of the external clock. The PLL of the LTC7892 is guaranteed to lock to an external clock source whose frequency is between 100kHz and 3MHz. The PLLIN/SPREAD pin is Transistor-transistor logic (TTL) compatible with thresholds of 1.6V (rising) and 1.1V (falling) and is guaranteed to operate with a clock signal swing of 0.5V to 2.2V. Output Overvoltage Protection The LTC7892 has an overvoltage comparator for each channel that guards against transient overshoots and other more serious conditions that can cause output overvoltage. When the VFBx pin rises more than 10% above its regulation point of 1.2V, the bottom FET is turned off, and the inductor current is not allowed to reverse. Power Good The LTC7892 has a PGOODx pin for each channel that is connected to an open drain of an internal N-channel MOSFET. The MOSFET turns on and pulls the PGOODx pin low when the VFBx voltage is not within ±10% of the 1.2V reference. The PGOODx pin is also pulled low when the RUNx pin is low (shut down). When the VFBx voltage is within the ±10% requirement, the MOSFET is turned off, and the PGOODx pin is allowed to be pulled up by an external resistor to a source no greater than 6V, such as INTVCC. When LTC7892 is operated in a 2-phase single output configuration, the output voltage is sensed by the VFB1 pin only. The PGOOD1 pin is pulled low when the VFB1 voltage is not within ±10% of the 1.2V reference. The PGOOD2 should be left floating. |
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