DS1WM

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OPERATION – FLAGS AND INTERRUPTS

Flags from current status, transmit, receive, and 1-Wire reset operations are located in the Interrupt

Register. The Presence Detect flag (PD), OW_LOW, and OW_SHORT are cleared when the Interrupt

Register is read. The other flags are cleared automatically when the Transmit and Receive Buffers are

written to or read from. All of these flags can generate an interrupt on the INTR pin if the corresponding

enable bit is set in the Interrupt Enable Register. To clear the INTR signal, the Interrupt Register must be

read. Reading the Interrupt Register always sets the INTR pin inactive even if all flags are not cleared.

Interrupt Register (Read Only)

Default: 0Eh

Addr. 02h

OW_LOW

OW_SHORT

RSRF

RBF

TEMT

TBE

PDR

PD

MSB

LSB

OW_LOW: One Wire Low. This flag will be set to 1 when the 1-Wire line is low while the master is in

idle signaling that a slave device has issued a presence pulse on the 1-Wire (DQ) line. A read to the

Interrupt Register will clear this bit.

OW_SHORT: One Wire Short. This flag will be set to a 1 when the 1-Wire line was low before the

master was able to send out the beginning of a reset or a time slot. When this flag is 0, it indicates that

the 1-Wire line was high as expected prior to all resets and time slots. A read to the Interrupt Register will

clear this bit.

RSRF: Receive Shift Register Full. This flag will be set to 1 when there is a byte of data waiting in the

Receive Shift Register. When this bit is 0, it indicates that the Receive Shift Register is either empty or

currently receiving data. This bit will be cleared by the hardware when data in the Receive Shift Register

is transferred to the Receive Buffer. A read to the Interrupt Register will have no effect on this bit.

RBF: Receive Buffer Full. This flag will be set to 1 when there is a byte of data waiting to be read in the

Receive Buffer. When this bit is 0, it indicates that the Receive Buffer has no new data to be read. This

bit will be cleared when the byte is read from the Receive Buffer. A read to the Interrupt Flag Register

will have no effect on this bit. However, following a read of the Interrupt Register, while Enable Receive

Buffer Full Interrupt (ERBF) is set to 1, if the ERBF is not cleared and the value is not read from the

Receive Buffer, the interrupt will fire again.

TEMT: Transmit Shift Register Empty. This flag will be set to 1 when there is nothing in the Transmit

Shift Register and it is ready to receive the next byte of data to be transmitted from the Transmit Buffer.

When this bit is 0, it indicates that the Transmit Shift Register is busy sending out data. This bit is cleared

when data is transferred from the Transmit Buffer to the Transmit Shift Register. A read to the Interrupt

Register will have no effect on this bit.

TBE: Transmit Buffer Empty. This flag will be set to 1 when there is nothing in the Transmit Buffer and

it is ready to receive the next byte of data. When it is 0, it indicates that the Transmit Buffer is waiting for

the Transmit Shift Register to finish sending its current data before updating it. This bit is cleared when

data is written to the Transmit Buffer. A read to the Interrupt Register will have no effect on this bit.

PDR: Presence Detect Result. When a presence detect interrupt occurs, this bit will reflect the result of

the presence detect read – it will be 0 if a slave was found, or 1 if no part was found. A read to the

Interrupt Register will have no effect on this bit.

PD: Presence Detect. After a 1-Wire Reset has been issued, this flag will be set to 1 after the appropriate

amount of time for a presence detect pulse to have occurred. This flag will be 0 when the master has not

issued a 1-Wire Reset since the previous read of the Interrupt Register. This bit is cleared when the

Interrupt Register is read.