DS1WM

19 of 20

0.5 – August 24, 1999

1. In Section 1.0, changed “four registers” to “five registers”, to reflect current actual register count.

Note that receive and transmit registers are actually 1 register in the memory map.

2. Corrected block diagram to reflect 1.25µs timebase maximum.

3. Removed voltage specifications on logic high and low in Section 3.0, as these will be process-

specific.

4. Changed lower clock rate to 3.2MHz in the text description of the CLK pin.

master. The master will wait for up to 60µs to detect a falling edge; but if the edge occurs before

60µs, the master will wait 30µs after that edge to sample the data line to read the presence detect.

7. Fixed errors in timing specification table left over from the change to maximum internal timebase

period of 1.25µs.

0.6 – September 17, 1999

1. TBE and TEMT default states changed to 1 instead of 0, to reflect their actual state (empty) upon a

master reset.

1.0 – September 20, 1999

1. Changed the operation of the interrupt register. The RBF and RSRF flags are no longer

automatically cleared when a read operation is performed on the Interrupt Register. Doing so

would allow for data to be overwritten if the interrupt handler did not do a read of the receive

buffer immediately following the interrupt. These flags are now cleared when the data has actually

been read or shifted out.

2. Revision 1.000 of the VHDL code is complete, and this specification reflects the current operation of

that VHDL code. Thus, the revision number for this specification is changed to 1.0 and t OPERATION

31 October, 1999.

3. Revision 1.2 of the datasheet complete. Format has been changed to look like a standard DS datasheet.

Verilog version of the code is also complete. Both types undergoing testing on the bench.

21 November, 2000.

1. Receive Data no longer double buffered. Data is now immediately transferred to the Receive Buffer

even if already full.

2. Shift Register flags removed from the Interrupt and Interrupt Enable registers. No longer needed.

3. DQO and DQI added to the Command Register to control the bus directly.

4. Low pulse widths for a write 1 changed from 1µs to 2µs and for a write 0 from 75µs to 30µs.

5. Interrupt Register – Flags are no longer cleared on a read except for PD. INTR is set inactive

automatically on a read.

6. Gate count updated to 1492 to reflect newest revision on page 1.

13 September, 2001.

1. Updated specification to match the changes made to the Verilog version of the master in the

DS80C400. These changes have been placed into the Verilog standalone version for which this

document pertains.

2. Added new interrupts, the Control register, and all of the features included in the Control register.

18 August, 2004

1. Updated Verilog version to not hardwire IAS bit. Was hard-wired to active-low. It now performs as

specified in this datasheet.

2. VHDL Version updated to match this new spec, version number in source updated to 2.0.