DS1WM

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OD: Overdrive. Setting this bit to a 1 will place the master into Overdrive mode that effectively changes

the master’s 1-Wire timings to match those outlined for Overdrive in the Book of iButton Standards.

Clearing this bit to a 0 leaves the master operating in standard mode speed.

BIT_CTL: Bit Control. Setting this bit to a 1 will place the master into its “Bit Banging” mode of

operation. In this mode, only the least significant bit of the Transmit/Receive register would be

sent/received before enabling the interrupt flags that signal the end of the transmission. Clearing this bit

to 0 leaves the master operating in full byte boundaries.

STP_SPLY: Strong Pull-up Supply. Setting this bit to a 1 while STPEN is also set to a 1 will enable the

STPZ output while the master is in an IDLE state. This will provide a stiff supply to devices requiring

high current during operations. Clearing this bit to a 0 disables the STPZ output while the master is in an

IDLE state. The STP_SPLY bit is a don’t care if STPEN is set to a 0.

STPEN: Strong Pull-up Enable. Setting this bit to a 1 enables the strong pull-up output enable (STPZ)

pin’s functionality which allows this output pin to enable an external strong pull-up any time the master is

not pulling the line low or waiting to read a value from a slave device. This functionality is used for

meeting the recovery time requirement in Overdrive mode and long-line standard communications.

Clearing this bit to a 0 will disable the STPZ output pin.

EN_FOW: Enable Force One Wire. Setting this bit to a 1 will enable the functionality of the Force One

Wire (FOW) register bit in the Command Register. Clearing this bit will disable the functionality of the

FOW bit.

PPM: Presence Pulse Masking Mode. Setting this bit to a 1 will enable Presence Pulse Masking Mode.

This mode causes the master to initiate the falling edge of a presence pulse during a 1-Wire Reset before

the fastest slave would initiate one. This enables the master to prevent the larger amount of ringing

caused by the slave devices when initiating a low on the DQ line. If the PPM bit is set, the PDR result bit

in the Interrupt Register will always be set to a 0 showing that a slave device was on the line even if there

were none. Clearing this bit to a 0 disables the Presence Pulse Masking Mode.

LLM: Long Line Mode. Setting this bit to a 1 will enable Long Line Mode timings on the 1-Wire line

during standard mode communications. This mode effectively moves the write one release, the data

sampling, and the time slot recovery times out to roughly 8µs, 22µs, and 14µs respectively. This provides

a less strict environment for long line transmissions. Clearing this bit to 0 leaves the write one release,

the data sampling, and the time slot recovery times at roughly 5µs, 15µs, and 7µs respectively.