DS1WM

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OPERATION – FLAGS AND INTERRUPTS (continued)

The Interrupt Enable Register allows the system programmer to specify the source of interrupts which

will cause the INTR pin to be active, and to define the active state for the INTR pin. When a Master Reset

is received all bits in this register are cleared to 0 disabling all interrupt sources and setting the active

state of the INTR pin to LOW. This means the INTR pin will be pulled high since all interrupts are

disabled. The INTR pin is reset to an inactive state by reading the Interrupt Register.

Interrupt Enable Register (Read / Write)

Default: 00h

Addr. 03h

EOWL

EOWSH

ERSF

ERBF

ETMT

ETBE

IAS

EPD

MSB

LSB

EOWL: Enable One Wire Low Interrupt. Setting this bit to a 1 enables the One Wire Low Interrupt. If

set, INTR will be asserted when the OW_LOW flag is set. Clearing this bit disables OW_LOW as an

active interrupt source.

EOWSH: Enable One Wire Short Interrupt. Setting this bit to a 1 enables the One Wire Short Interrupt.

If set, INTR will be asserted when the OW_SHORT flag is set. Clearing this bit disables OW_SHORT as

an active interrupt source.

ERSF: Enable Receive Shift Register Full Interrupt. Setting this bit to a 1 enables the Receive Shift

Register Full Interrupt. If set, INTR will be asserted when the RSRF flag is set. Clearing this bit disables

RSRF as an active interrupt source.

ERBF: Enable Receive Buffer Full Interrupt. Setting this bit to a 1 enables the Receive Buffer Full

Interrupt. If set, INTR will be asserted when the RBF flag is set. Clearing this bit disables RBF as an

active interrupt source.

ETMT: Enable Transmit Shift Register Empty Interrupt. Setting this bit to a 1 enables the Transmit Shift

Register Empty Interrupt. If set, INTR will be asserted when the TEMT flag is set. Clearing this bit

disables TEMT as an active interrupt source.

ETBE: Enable Transmit Buffer Empty Interrupt. Setting this bit to a 1 enables the Transmit Buffer

Empty Interrupt. If set, INTR will be asserted when the TBE flag is set. Clearing this bit disables TBE as

an active interrupt source.

IAS: INTR Active State. This bit determines the active state for the INTR pin. If this bit is a 1, the INTR

pin is active high; if it is a 0, the INTR pin is active low.

EPD: Enable Presence Detect Interrupt. Setting this bit to a 1 enables the Presence Detect Interrupt. If set,

INTR will be asserted when the PD flag is set. Clearing this bit disables PD as an active interrupt source.