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ROM command see [1]. In addition to these two functions, the Command Register contains two bits to

bypass the 1-Wire Master features and control the 1-Wire bus directly.

Command Register (Read/Write)

Default: 08h

Addr. 00h

X

X

X

X

OW_IN

FOW

SRA

1WR

MSB

LSB

Bit 3 - OW_IN: OW Input. This bit always reflects the current state of the 1-Wire line.

Bit 2 - FOW: Force One Wire. This bit can be used to bypass 1-Wire Master operations and drive the bus

directly if needed. Setting this bit high will drive the bus low until it is cleared or the 1-Wire Master reset.

While the 1-Wire bus is held low no other 1-Wire Master operations will function. By controlling the

length of time this bit is set and the point when the line is sampled, any 1-Wire communication can be

generated by the host controller. To prevent accidental writes to the bus, the EN_FOW bit in the

CONTROL register must be set to a 1 before the FOW bit will function. This bit is cleared to a 0 on

power-up or master reset.

Bit 1 - SRA: Search ROM Accelerator. When this bit is set, the 1-Wire Master will switch to Search

ROM Accelerator mode. (See “Search ROM Accelerator Description” for the rest of the function

description.) When this bit is set to 0, the master will function in its normal mode. This bit is cleared to 0

on a power-up or master reset.

Bit 0 - 1WR: 1-Wire Reset. If this bit is set a reset will be generated on the 1-Wire bus. Setting this bit

automatically clears the SRA bit. The 1WR bit will be automatically cleared as soon as the 1-Wire reset

completes. The 1-Wire Master will set the Presence Detect interrupt flag (PD) when the reset is complete

and sufficient time for a presence detect to occur has passed. The result of the presence detect will be

placed in the interrupt register bit PDR. If a presence detect pulse was received PDR will be cleared,

otherwise it will be set.

Search ROM Accelerator Description

The Search ROM Accelerator Mode presupposes that a Reset followed by the Search ROM command

(0xF0h) has already been issued on the 1-Wire bus. For details on how the Search ROM is actually done

in the 1-Wire system, please see [1]. Simply put, the algorithm specifies that the bus master reads two bits

(a bit and its complement), then writes a bit to specify which devices should remain on the bus for further

processing.

After the 1-Wire Master is placed in Search ROM Accelerator mode, the CPU must send 16 bytes to

complete a single Search ROM pass on the 1-Wire bus. These bytes are constructed as follows:

First byte

7

6

5

4

3

2

1

0

16

7

6

5

4

3

2

1

0

In this scheme, the index (values from 0 to 63, “n”) designates the position of the bit in the ROM ID of a

1-Wire device. The character “x” marks bits that act as a filler and do not require a specific value (don’t

care bits). The character “r” specifies the selected bit value to write at that particular bit in case of a

conflict during the execution of the ROM search.