TMP88CS38 datasheet(111/226 Pages) TOSHIBA

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TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-111

Remote Control Receive Control Register 1

RXCR1

(00FE8H)

RCCK

RPOLS

EINT

RNC

(Initial value: 0000 0000)

RCCK

8-bit up counter source clock

select

00: fc/2

6 (Hz)

01: fc/2

10: fc/2

11: fc/2

RPOLS

Remote control signal polarity

select

Positive

Negative

EINT

Interrupt source select

00: Rising edge

01: Falling edge (at RPOLS

= 0)

10: Rising/falling edge

11: 8-bit receive end

RNC

Noise canceler noise

eiminating time select

001: 2

2/fc

× 7 − 1/fc (s)

010: 2

5/fc

× 7 − 1/fc

011: 2

6/fc

× 7 − 1/fc

100: 2

7/fc

× 7 − 1/fc

101: 2

8/fc

× 7 − 1/fc

110: 2

10/fc

× 7 − 1/fc

111: 2

12/fc

× 7 − 1/fc

000: Noise canceler disable

R/W

Note 1:

fc: High-frequency clock [Hz]

Note 2:

After reset, RPOLS do not change the set value in the receiving remote control signal. For setting interrupt

edge and measurement data, use EINT and RMM.

Remote Control Receive Control Register 2

RXCR2

(00FE9H)

CREGA

RCS

RMCEN

RMM

(Initial value: 0000 0000)

CREGA

Setting of detect time for

match with 8-bit up counter

upper 4 bits

Match detect time (Tth)

= 16 × CREGA/RCCK [s]

CREGA

= 0H to FH

Example:

CREGA

= 2H, RCCK = fc/26 [Hz], at fc = 16 MHz,

DV1CK

= 1

Tth

= 128 [μs]

RCS

8-bit up counter start control

Stop and counter clear

Start

RMCEN

Remote control signal

preprocesser enable/disable

Disable

Enable

RMM

Measurement mode select

(invalid when EINT

= “10”)

00:

01:

10:

11:

R/W

Note 1:

fc: High-frequency clock [Hz]

Note 2:

When an interrupt source is set for rising/falling edge, low and high widths are forcibly measured

separately.

Note 3:

Set CREGA (0H to FH) before EINT sets to 8-bit receive end.

Figure 2.10.2 Remote Control Receive Control Register 1, 2

Refer to Talbe 2.10.1

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