BMP581 datasheet(25/75 Pages) BOSCH

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Bosch Sensortec | BST-BMP581-DS004-11

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Document number: BST-BMP581-DS004-11

as well as in the event of applications for industrial property rights

4.6.4 FIFO configuration changes

The FIFO is flushed on any of the following conditions:



a change in the sensor configuration:

o OSR_CONFIG.osr_t

o OSR_CONFIG.osr_p

o ODR_CONFIG.odr

o ODR_CONFIG.pwr_mode



a change in the frame configuration:

o FIFO_SEL.fifo_frame_sel

o FIFO_SEL.cfg_fifo_dec_sel

The flush will empty the FIFO, reset the FIFO_COUNT register, and clear the interrupt conditions.

The completion of the FIFO flush is finished within treconf, or treconf_deep if the device is in deep sleep.The FIFO_COUNT

should not be read before the flush has been finished, as the result may be inconsistent.

If the register FIFO_CONFIG_fifo_threshold is written, the resulting interrupt status bits will be immediately updated

according to the new threshold.

The register FIFO_SEL must only be changed in STANDBY mode.

A change of FIFO_SEL.cfg_fifo_dec_sel during NORMAL or CONTINUOUS mode will only be applied after a transition

to STANDBY. It will also not flush the FIFO.

A change of FIFO_SEL.fifo_frame_sel during NORMAL or CONTINOUS mode may be ignored as well, depending on

if the press_en bit is also changed.

4.7Interrupts

The BMP581 provides an interrupt pin (INT), which allows to signal certain events to the host processor. Different

events can be mapped to the interrupt pin, which all are processed with a logical OR.

BMP581 also supports I3C‘s in-band interrupt (IBI). This is allows the use of interrupt functionality without the need of

a dedicated INT signal line. For documentation of the I3C IBI functionality, see Chapter 4.7.2 "I3C In-band Interrupts".

The available interrupts are listed below, and will be detailed in following subsections:



FIFO watermark interrupt



FIFO full interrupt



Data ready interrupt



Pressure out-of-range interrupt



Power-on reset (POR) interrupt

4.7.1 Interrupt enabling

The individual interrupts sources can be enabled in the INT_SOURCE register. An exception is the POR interrupt,

which is always enabled. With enabled interrupt sources:



their individual status is available from the INT_STATUS register,



I3C in-band interrupts can be used (see Chapter 4.7.2 "I3C In-band Interrupts"), and



the interrupt pin can be used, see Chapter 3.7.3.

4.7.2 Interrupt sources

4.7.2.1

FIFO interrupts

The FIFO provides two sources of interrupts:



FIFO full: The fill level is at the maximum number of frames. This means 16 PT frames or 32 P or T frames,

depending on the configuration of the FIFO.



FIFO threshold reached: The fill level is at or above the FIFO threshold level (see Chapter 3.6.1).

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