ADAQ4216BBCZ datasheet(39/63 Pages) AD

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Data Sheet

ADAQ4216

APPLICATIONS INFORMATION

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Rev. A | 39 of 63

ADC RESET

The ADAQ4216 provides two options for performing an ADC reset

using the serial interface. A hardware reset is initiated by pulsing

the voltage on the RST pin low. A software reset is initiated by

setting both the SW_RESET and SW_RESETX bits in the Interface

Configuration A register to 1 in the same write instruction (for more

details, see the Interface Configuration A Register section).

Performing a hardware or software reset asserts the RESET_OC-

CURRED bit in the digital diagnostics register (for more details, see

the Digital Diagnostics Register section). The RESET_OCCURRED

bit is cleared by writing the bit with a 1. RESET_OCCURRED can

be used by the digital host to confirm that the ADAQ4216 has

executed a device reset.

The ADAQ4216 is designed to generate a power-on reset (POR)

when VDD_5V and VDD_1.8V are first applied. A POR resets

the state of the user configuration registers and asserts the RE-

SET_OCCURRED bit. If VDD_5V or VDD_1.8V drops below its

specified operating range, a POR occurs. It is recommended to

perform a hardware or software reset after a POR.

Figure 100 shows the timing diagram for performing an ADC reset

using the RST input. The minimum RST pulse width is 50ns,

represented by tRESETPW in Figure 100 and Table 1. A reset must

be performed no sooner than 3ms after the power supplies are valid

and stable (this delay is represented by tRESET_DELAY in Figure 100

and Table 1).

After a hardware or software reset, no SPI commands or conver-

sions can be started for 750µs.

Figure 100. POR Timing

POWER SUPPLIES

The recommended power-up sequence for the supply pins of the

ADAQ4216 is shown in Figure 101. The recommended sequence

is power up the PGIA (VDDH and VSSH) first, then the FDA

(VDD_FDA and VSS_FDA) along with the supplies of the ADC

(VDD_5V, VLDO and VIO), then bring up the reference voltage

(REFIN) and lastly turning on the input signal at INP and INN pins.

Care must be taken to adhere to the maximum voltage relationships

described in the Absolute Maximum Ratings section.

Figure 101. Power Supply Sequence

The voltage range for the VDD_5V supply depends on the chosen

reference voltage (see the parameter Internal Reference Buffer in

Table 1). Figure 102 shows the minimum and maximum values for

VDD_5V with respect to REFIN. VDD_5V voltage values above the

maximum or below the minimum result in either damage to the

device or degraded performance.

Figure 102. VDD_5V Minimum and Maximum Values for REFIN

The ADAQ4216 has a POR circuit that resets the ADAQ4216 at

initial power-up or whenever VDD_5V or VDD_1.8V drops below its

specified operating range.

Note that the VDD_5V and the VLDO supplies have internal 1µF

bypass capacitors inside the package, VIO has an internal 0.2µF

bypass capacitor, while VDDH, VSSH, VDD_FDA, VSS_FDA, and

VDD have internal 0.1µF bypass capacitor. These internal capaci-

tors reduce BOM count and solution size. If the bulk-supply bypass

ADAQ4216BBCZ Datasheet(PDF) 39 Page - Analog Devices

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