ADAQ4216BBCZ datasheet(51/63 Pages) AD

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Data Sheet

ADAQ4216

SERIAL INTERFACE

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Rev. A | 51 of 63

Echo Clock Timing Diagrams

1-Lane, SDR Mode, Echo Clock Mode

Figure 7 shows the timing relationships for SDR mode (1-bit per

SCK period) in 1-lane echo clock mode. The timing relationships

between the signals apply to both 16-bit and 32-bit sample word

formats.

SCKOUT is a delayed version of the incoming SCK. The delay

(tDSDO) has a maximum value of 5.6ns (at VIO > 1.71V). Changes in

SDOx logic states are aligned to the rising edges of SCKOUT. The

clock and data edge alignments are the same for 1-lane, 2-lane,

and 4-lane output data modes.

1-Lane, DDR Mode, Echo Clock Mode

Figure 8 shows the timing relationships for DDR mode (2-bit transi-

tions per SCKOUT period) in 1-lane mode echo clock mode. The

timing relationships between the signals apply to both 16-bit and

32-bit sample word formats.

Similar to SDR mode, SCKOUT is a delayed version of the incom-

ing SCK. Changes in SDOx logic states are aligned to both rising

and falling edges of SCKOUT.

Host Clock Mode Timing

1-Lane, Host Clock Mode, SDR

Figure 9 shows the timing relationships for host clock mode when

using SDR mode and 1-lane mode. Similar to echo clock mode,

the clock rising edges are aligned to the data bit transitions. The

frequency of SCKOUT signal is controlled by the OSC_DIV value

programmed in the internal oscillator register (for more details, see

the Internal Oscillator Register section). Note that when the output

data format is 16-bit differential (OUT_DATA_MD = 000 in the

Modes Register), each 16-bit sample is padded with eight zeros,

which makes the total word length to 24 bits. The host processor

discards these bits when processing the data.

1-Lane, Host Clock Mode, DDR

Figure 10 shows the timing relationships for host clock mode when

using DDR. Similar to echo clock mode, the rising and falling clock

edges are aligned to the data bit transitions. The frequency of

SCKOUT signal is controlled by the OSC_DIV value programmed

in the internal oscillator register (for more details, see the Internal

Oscillator Register section). Note that when the output data format

is 16-bit differential (OUT_DATA_MD = 000 in the Modes Register),

each 16-bit sample is padded with eight zeros, which makes the

total word length to 24 bits. The host processor discards these bits

when processing the data.

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