ADAQ4216BBCZ datasheet(2/63 Pages) AD

2 / 63 page

Data Sheet

ADAQ4216

TABLE OF CONTENTS

analog.com

Rev. A | 2 of 63

Features................................................................ 1

Applications........................................................... 1

Functional Block Diagram......................................1

General Description...............................................3

Specifications........................................................ 4

Timing Specifications......................................... 7

Absolute Maximum Ratings.................................13

Thermal Resistance......................................... 13

Electrostatic Discharge (ESD) Ratings.............13

ESD Caution.....................................................13

Pin Configurations and Function Descriptions.....14

Typical Performance Characteristics................... 16

Terminology......................................................... 29

Theory of Operation.............................................30

Overview.......................................................... 30

Transfer Function............................................. 30

Signal Chain Operation.................................... 31

Digital Sample Processing Features................ 31

Applications Information...................................... 33

Typical Application Diagram............................. 33

Reference Circuitry Design ............................. 38

ADC Reset....................................................... 39

Power Supplies................................................ 39

Serial Interface.................................................... 41

SPI Signals.......................................................41

Sample Conversion Timing and Data

Transfer.......................................................... 43

Clocking Modes ...............................................44

Data Clocking Requirements and Timing.........47

Layout Guidelines................................................52

Registers............................................................. 53

Interface Configuration A Register................... 54

Interface Configuration B Register................... 54

Device Configuration Register..........................55

Chip Type Register...........................................55

Product ID Low Register.................................. 55

Product ID High Register..................................55

Chip Grade Register.........................................56

Scratch Pad Register....................................... 56

SPI Revision Register...................................... 56

Vendor ID Low Register................................... 57

Vendor ID High Register...................................57

Stream Mode Register..................................... 57

Interface Status A Register.............................. 57

EXIT Configuration Mode Register...................58

Averaging Mode Register.................................58

Offset Registers................................................58

Gain Registers..................................................59

Modes Register................................................ 59

Internal Oscillator Register............................... 60

Output Driver Register......................................60

Test Pattern Registers...................................... 61

Digital Diagnostics Register............................. 62

Digital Errors Register...................................... 62

Outline Dimensions............................................. 63

Ordering Guide.................................................63

Evaluation Boards............................................ 63

REVISION HISTORY

5/2025—Rev. 0 to Rev. A

Change to Features Section............................................................................................................................ 1

Changes to Input Bias Current Parameter and Input Offset Current Parameter, Table 1................................ 4

Changes to Figure 61 and Figure 64............................................................................................................. 24

Added Figure 65; Renumbered Sequentially................................................................................................. 24

Changes to Figure 79 to Figure 83................................................................................................................ 27

Moved Figure 84; Renumbered Sequentially.................................................................................................28

Change to Typical Application Diagram Section............................................................................................ 33

1/2025—Revision 0: Initial Version

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