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BMP585 Datasheet(PDF) 61 Page - Bosch Sensortec GmbH |
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BMP585 Datasheet(HTML) 61 Page - Bosch Sensortec GmbH |
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61 / 71 page ![]() Bosch Sensortec | BST-BMP585-DS003-02 61 | 71 © Bosch Sensortec GmbH 2023 | All rights reserved, also regarding any disposal, exploitation, reproduction, editing, distribution, Document number: BST-BMP585-DS003-02 as well as in the event of applications for industrial property rights 0x16 15.000 Hz (Error = 0.00) 0x17 10.000 Hz (Error = 0.00) 0x18 5.000 Hz (Error = 0.00) 0x19 4.000 Hz (Error = 0.00) 0x1A 3.000 Hz (Error = 0.00) 0x1B 2.000 Hz (Error = 0.00) 0x1C 1.000 Hz (Error = 0.00) 0x1D 0.500 Hz (Error = 0.00) 0x1E 0.250 Hz (Error = 0.00) 0x1F 0.125 Hz (Error = 0.00) • deep_dis:(bit offset: 7) If asserted, disables the deep standby (Note: This field cannot be changed during an ongoing P/T conversion.) 8.35 Register (0x38) Effective over-sampling rate (OSR) configuration Bit 7 6 5 4 3 2 1 0 Read/Write R R R R R R R R Reset Value 0 0 0 0 0 0 0 0 Content odr_is_... reserved_6 osr_p_eff osr_t_eff • osr_t_eff:(bit offset: 0) OSR_T effective selection. Effectively selected OSR for temperature. Please refer to OSR_- CONFIG for encodings. • osr_p_eff:(bit offset: 3) OSR_P effective selection. Effectively selected OSR for pressure. Please refer to OSR_- CONFIG for encodings. • reserved_6:(bit offset: 6) reserved • odr_is_valid:(bit offset: 7) If asserted, the ODR parametrization is valid (This is checked on every change in ODR and OSR configuration registers.) • The values that are effective when the configured ODR might be invalid in combination with OSR configuration This is observable with the ODR_CONFIG.flag odr_is_valid 8.36 Register (0x7E) Command Register Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 0 0 0 0 0 0 0 0 Content cmd • cmd:(bit offset: 0) Available commands (Note: Register will always read as 0x00): no other values must be written to this register Value Description 0xB6 Triggers a reset, all user configuration settings are overwritten with their default state. If this register is set using I2C, an ACK will NOT be transmitted to the host 0xA5 Last CMD in the sequence 0x5D, 0xA5 which enables the read of the NVM. If another CMD is sent within the sequence, the sequence for triggering the NVM read is reset. 0xA0 Last CMD in the sequence 0x5D, 0xA0 which enables the write of the NVM. If another CMD is sent within the sequence, the sequence for triggering the NVM programming is reset. |
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