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BMP585 Datasheet(PDF) 37 Page - Bosch Sensortec GmbH |
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BMP585 Datasheet(HTML) 37 Page - Bosch Sensortec GmbH |
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37 / 71 page ![]() Bosch Sensortec | BST-BMP585-DS003-02 37 | 71 © Bosch Sensortec GmbH 2023 | All rights reserved, also regarding any disposal, exploitation, reproduction, editing, distribution, Document number: BST-BMP585-DS003-02 as well as in the event of applications for industrial property rights 5.6 I²C protocol BMP585 supports the following I²C modes: normal mode (100 kHz) fast mode (100 - 400 kHz) fast mode plus (400 kHz - 1 MHz) The I²C slave address of BMP585 is 7'h46 for SDO = 1'b0 and 7'h47 for SDO = 1'b1. SDO must not be floating when I²C is used, otherwise the I²C device address is undefined. CSB has an integrated pull-up resistor, which can be enabled in I²C and I3C mode by setting DRIVE_CONFIG.i2c_csb_pup_en. 5.6.1 I²C write operation I²C write operation supports single-byte as well as multi-byte (burst) writing. Figure 13 depicts the I²C write transfer for single-byte write operation. The transfer begins with a start condition generated by the host, followed by 7 bit slave address and a write bit (R/W = 1'b0). The slave sends an acknowledge bit (ACK = 1'b0) and releases the bus. Subsequently the host is expected to send the register address. Only the first 7 bit (right aligned) are the valid address bit and the MSB is ignored. The slave shall again acknowledge the transmission and wait for the 8 bit data, which shall be written to the specified register address. After slave acknowledges the data byte, the host generates a stop signal and terminates the writing protocol. Figure 13: I²C single-byte write BMP585 also supports multi-byte write operation in I2C mode. The multi-byte write telegram is depicted in Figure 14. The telegram begins with a start condition generated by the host, followed by 7 bit slave address and a write bit (R/W = 1'b0). The slave sends an acknowledge bit (ACK = 1'b0) and releases the bus. Subsequently the host sends the one byte register address. Only 7 bit (right aligned) are the valid address bits and the MSB shall be ignored. The slave shall again acknowledge the transmission and wait for several 8 bit wide data words. The first data word is written to the specified register address. The register address pointer is automatically incremented for each data word. Each received data word is written to the register referenced by the current register address pointer. The slave acknowledges each data byte. When no more data words need to be written, the host generates a stop signal and terminates the writing protocol. |
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