BMP585 datasheet(27/71 Pages) BOSCH

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Bosch Sensortec

| BST-BMP585-DS003-02

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Document number: BST-BMP585-DS003-02

as well as in the event of applications for industrial property rights

4.7.2.4

Power-on reset interrupt

The power-on rest (POR) interrupt is triggered each time the BMP585 comes out of a power-up reset. This can happen if

the supply to the device is ramped up, or if the supply was so instable that the BMP585 performed a brown-out with

subsequent power-up reset. The POR interrupt signals that the BMP585 is ready to use.

POR interrupts are not supported with I3C IBI, as the device is not in a state where I3C is initialized after power-up reset.

Also, the interrupt pin will not flag a POR interrupt, as the interrupt pin is disabled after power-up.

The status of the interrupt can be read from INT_STATUS.por. A read of the INT_STATUS will clear the status.

4.7.3 Interrupt pin

The BMP585 provides an interrupt pin (INT), which allows to signal certain events to the host processor.

4.7.3.1

Interrupt pin configuration

The behavior of the interrupt pin can be configured in INT_CONFIG with these fields:



int_mode: The interrupt mode can be „pulsed“ or „latched“. Latching determines when an interrupt is released (see

section 4.7.3.2 for details)



int_pol: The interrupt polarity can be configured to be either „active high“ or „active low“



int_od: The interrupt pin can be configured to be „open-drain“ or push-pull“



int_en: The interrupt pin can be enabled. With enabled interrupt pin, all interrupt sources configured in

INT_-SOURCE will be OR’ed on the interrupt pin.

4.7.3.2

Interrupt Timings

Interrupt timings depend strongly on the int_mode setting:

Pulsed mode. In the pulsed mode the INT pin creates a pulse on the interrupt pin, each time an interrupt condition changes from

FALSE to TRUE, and the interrupt source is enabled in INT_SOURCE.

Figure 5 shows the timing of pulsed mode.

The pulse length is tint_pulse. Between two pulses, there is a minimum gap of tint_deassert in which the pin will stay de-

asserted.

Figure 5: INT pin timing in pulsed mode

Latched Mode. In latched mode, the INT pin is asserted as long as an interrupt condition is TRUE, and the interrupt

source is enabled in INT_SOURCE. Between two adjacent assertions if the INT pin, there is a minimum gap of tint_deassert.

Figure 6 shows the timing of latched mode.

The de-assertion of the INT pin in latched mode depends is handled in the following way:



FIFO interrupts will be de-asserted when the interrupt condition does not apply any more. There is no dependency

on the setting of INT_STATUS.

BMP585 Datasheet(PDF) 27 Page - Bosch Sensortec GmbH

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