ADF41510 datasheet(12/29 Pages) AD

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Data Sheet

ADF41510

THEORY OF OPERATION

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(IBLEED/ICP) × tPFD

(4)

LD_COUNT can range from 2 counts to 8192 counts. The fast-

est lock indication requires two measurement cycles (20 ns with

100 MHz reference, R = 1, and LD_CLK_SEL = 1). In practice,

the lock indication takes much longer because of the loop filter on

the phase comparator. When LD_CLK_SEL = 0, a minimum 64

measurements are required (640 ns).

READBACK

In this mode, the MUXOUT line concurrently transfers 32 bits of the

previous written register value while clocking in 32 bits of write data.

To read back a specific register, chip revision code, or bit pattern,

write 1000b to Bits[31:28], Register 12. Bits[19:14] in Register 12

set the data that is output from the MUXOUT pin when in readback

mode.

To prevent spurious writes, the DATA pin must be held at logic low

while a readback is taking place.

INPUT SHIFT REGISTERS

The ADF41510 contains a programmable digital block. Data is

clocked into the 32-bit shift register on each rising edge of CLK.

The data is clocked in MSB first. Data is transferred from the

shift register to the chosen register on the rising edge of LE. The

destination latch is determined by the state of the four control bits

(C4, C3, C2, and C1) in the shift register. The following are the four

LSBs: DB3, DB2, DB1, and DB0. The truth table for these bits is

shown in Table 6. Figure 18 through Figure 20 show a summary of

how the registers are programmed.

PROGRAM MODES

Table 6 and Figure 21 through Figure 34 show how to set up the

program modes in the ADF41510.

Several settings in the ADF41510 are double buffered. These set-

tings include MOD2, FRAC1, FRAC2, R counter value, reference

doubler, CP current setting, RDIV2, phase word, prescaler, and

CLK1 divider. Two events must occur before the device uses a new

value for any of the double buffered settings. First, the new value

is latched into the device by writing to the appropriate register. Sec-

ond, a new write must be performed on Register 0. For example,

updating the FRAC1 value requires a write to Register 1 and a

write to Register 0. Write to Register 1 first, followed by the write to

0. Double buffering ensures that the bits written to Register 1 do not

take effect until after the write to Register 0.

Table 6. C4, C3, C2, and C1 Truth Table

Control Bits

R10

R11

R12

R13

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