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TIMING DIAGRAMS

SCL

SDA

t

(LOW)

t

R

t

F

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(BUF)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

P

S

S

P

TMP400

SBOS404 – DECEMBER 2007

reads from the same register are desired, it is not

Stop Data Transfer: A change in the state of the

necessary to continually send the Pointer Register

SDA line from low to high while the SCL line is high

bytes, because the TMP400 retains the Pointer

defines

a

STOP

condition.

Each

data

transfer

Register value until it is changed by the next write

terminates

with

a

repeated

START

or

STOP

operation. Note that register bytes are sent MSB first,

condition.

followed by the LSB.

Data Transfer: The number of data bytes transferred

between a START and a STOP condition is not

limited and is determined by the master device. The

receiver acknowledges the transfer of data.

Figure 13 to Figure 16 describe various operations on

the

TMP400.

Bus

definitions

are

given

below.

Acknowledge:

Each

receiving

device,

when

Parameters for Figure 13 are defined in Table 10.

addressed, is obliged to generate an Acknowledge

bit. A device that acknowledges must pull down the

Bus Idle: Both SDA and SCL lines remain high.

SDA line during the Acknowledge clock pulse in such

Start Data Transfer: A change in the state of the

a way that the SDA line is stable low during the high

SDA line, from high to low, while the SCL line is high,

period of the Acknowledge clock pulse. Setup and

defines a START condition. Each data transfer

hold times must be taken into account. On a master

initiates with a START condition.

receive, data transfer termination can be signaled by

the master generating a Not-Acknowledge on the last

byte that has been transmitted by the slave.

Figure 13. Two-Wire Timing Diagram

Table 10. Timing Diagram Definitions for Figure 13

FAST MODE

HIGH-SPEED MODE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

SCL Operating Frequency

0.001

0.4

0.001

3.4

MHz

Bus Free Time Between STOP and START Condition

600

160

ns

Hold time after repeated START condition.

100

100

ns

After this period, the first clock is generated.

Repeated START Condition Setup Time

100

100

ns

STOP Condition Setup Time

100

100

ns

Data Hold Time

ns

Data Setup Time

100

10

ns

SCL Clock LOW Period

1300

160

ns

SCL Clock HIGH Period

600

60

ns

Clock/Data Fall Time

300

ns

Clock/Data Rise Time

300

160

ns

for SCL

≤ 100kHz

1000

160

(1)

For cases with fall time of SCL less than 20ns and/or the rise time or fall time of SDA less than 20ns, the hold time should be greater

than 20ns.

(2)

For cases with fall time of SCL less than 10ns and/or the rise or fall time of SDA less than 10ns, the hold time should be greater than

10ns.

14

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