20

AT42QT1060 [DATASHEET]

9505H–AT42–04/2015

5.12

Address 22: LP Mode

LP Mode: this 8-bit value determines the number of 16 ms intervals between key measurements. Longer intervals

between measurements yield lower power consumption at the expense of slower response to touch.

A value of zero causes the device to enter SLEEP mode where no measurements are performed.

A value of 255 causes the device to enter Free-run mode where measurements are continuously performed without

entering a low power mode between measurements. This provides the fastest response time but also the highest

power consumption.

Default: 2 (32 ms between key acquisitions)

5.13

Address 23: I/O Mask

IO0 – IO6: these bits control the direction of the I/O pins. A 1 sets the pin as an output, a 0 as an input. See Section

5.24 on page 24 for I/O register precedence and example usage.

Default: 0 (all I/Os are set as inputs, when using the I2C-compatible mode)

(all I/Os are set as outputs (

0x7F), when using the standalone mode)

Table 5-12. LP Mode

Address

b7

b6

b5

b4

b3

b2

b1

b0

22

MSB

LSB

LP7 – 0

Mode

0

SLEEP

1

16 ms

2

32 ms

3

48 ms

4

64 ms

...

...

254

4.064 s

255

Free-run

Table 5-13. I/O Mask

Address

b7

b6

b5

b4

b3

b2

b1

b0

23

Reserved

IO6

IO5

IO4

IO3

IO2

IO1

IO0