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AT42QT1060 [DATASHEET]

9505H–AT42–04/2015

6.

The host must then send a STOP and a START condition followed by the slave address again but this time

accompanied by the READ bit.

7.

The device returns an ACK, followed by a data byte.

8.

The host must return either an ACK or NACK.

1.

If the host returns an ACK, the device subsequently transmits the data byte from the next address. Each

time a data byte is transmitted, the device automatically increments the internal address. The device

continues to return data bytes until the host responds with a NACK.

2.

If the host returns a NACK, it should then terminate the transfer by issuing the STOP condition.

9.

The device resets the internal address to the location indicated by the memory address sent to it previously.

Therefore, there is no need to send the memory address again when reading from the same location.

4.4

SDA, SCL

The I2C bus transmits data and clock with SDA and SCL respectively. They are open-drain; that is I2C master and

slave devices can only drive these lines low or leave them open. The termination resistors (not shown) pull the line

up to Vdd if no I2C-compatible device is pulling it down.

The termination resistors commonly range from 1 k

 to 10 k and should be chosen so that the rise times on SDA

and SCL meet the I2C specifications (1 µs maximum).

Standalone mode: if I2C-compatible communications are not required, then standalone mode can be enabled by

connecting SDA to Vss and SCL to Vdd. See Section 2.3 on page 6 for more information.