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AT42QT1060 [DATASHEET]

9505H–AT42–04/2015

A.5

Data Byte Format

All data bytes are 9 bits long, consisting of 8 data bits and an acknowledge bit. During a data transfer, the host

generates the clock and the START and STOP conditions, while the receiver is responsible for acknowledging the

reception. An acknowledge (ACK) is signaled by the receiver pulling the SDA line low during the ninth SCL cycle. If

the receiver leaves the SDA line high, a NACK is signaled.

Figure A-5.

Data Byte Format

A.6

Combining Address and Data Bytes into a Transmission

A transmission consists of a START condition, an SLA+R/W, one or more data bytes and a STOP condition. The

wired ANDing of the SCL line is used to implement handshaking between the host and the device. The device

extends the SCL low period by pulling the SCL line low whenever it needs extra time for processing between the

data transmissions.

Note: Each write or read cycle must end with a stop condition. The device may not respond correctly if a cycle is

terminated by a new start condition.

Figure A-6 shows a typical data transmission. Note that several data bytes can be transmitted between the

SLA+R/W and the STOP.

Figure A-6.

Byte Transmission

A.7

Data MSB

Data LSB

ACK

Aggregate

SDA

SCL from

Master

12

78

9

SDA from

Transmitter

SDA from

Receiver

Data Byte

Stop or

Data Byte

Next

SLA+R/W

Data MSB

Data LSB

ACK

12

78

9

Addr MSB

Addr LSB

R/W

ACK

SDA

SCL

START

12

78

9

SLA+RW

Data Byte

STOP