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AT42QT1060 [DATASHEET]

9505H–AT42–04/2015

Appendix A. I2C Basics

A.1

Interface Bus

The device communicates with the host over an I2C bus. The following sections give an overview of the bus; more

detailed information is available from www.i2C-bus.org. Devices are connected to the I2C bus as shown in Figure A-

1. Both bus lines are connected to Vdd via pull-up resistors. The bus drivers of all I

2C devices must be open-drain

type. This implements a wired AND function that allows any and all devices to drive the bus, one at a time. A low

level on the bus is generated when a device outputs a zero.

Figure A-1.

I

2C Interface Bus

A.2

Transferring Data Bits

Each data bit transferred on the bus is accompanied by a pulse on the clock line. The level of the data line must be

stable when the clock line is high; the only exception to this rule is for generating START and STOP conditions.

Figure A-2.

Data Transfer

Device 1

Device 2

Device 3

Device n

R1

R2

Vdd

SDA

SCL

SDA

SCL

Data Stable

Data Stable

Data Change