DDC232 datasheet(17/35 Pages) TI2

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ADCONV

IRST

ADRST

INT

End Integration Side A

Start Integration Side B

Side A

Data Ready

Side B

Data Ready

Side B

Side A

Side B

Side A

End Integration Side B

Start Integration Side A

End Integration Side A

Start Integration Side B

CONV

DVALID

A/D Conversion

Odd Channels (Internal)

A/D Conversion

Even Channels (Internal)

IRST

ADRST

ADCONV

DDC232

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SBAS331D – AUGUST 2004 – REVISED APRIL 2010

In Figure 11, the first state is Ncont state 8. The

Ncont modes described earlier in the Continuous and

DDC232 always powers up in the Ncont mode. In this

Noncontinuous Operational Modes section. DVALID

case, the first state is 8 because CONV is initially

goes low after CONV toggles in time tCMDR, indicating

low. After the first two states, Cont mode operation is

that data are ready to be retrieved.

reached and the states begin toggling between 4 and

See Figure 12 for the timing diagram of the internal

5. From now on, the input is being continuously

operations

occurring

during

Continuous

mode

integrated, either on side A or side B. The time

operation. Table 10 gives the timing specifications of

needed for the m/r/az cycle, tMRAZ, is the same time

the internal operations occurring during Continuous

that determines the boundary between the Cont and

mode operation.

Figure 12. Internal Operation in Continuous Mode Timing

Table 10. Timing Characteristics for the Internal Operation in Continuous Mode

DDC232C

DDC232CK

(CLK = 5MHz, Clk_4x = 0)

(CLK = 10MHz, Clk_4x = 0)

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

tINT

Integration Period (continuous mode)

320

1,000,000

160

1,000,000

tADCONV

A/D Conversion Time (internally controlled)

135.6

tADRST

A/D Conversion Reset Time (internally controlled)

3.2

2.2

tIRST

Integrator Reset Time (internally controlled)

21.8

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