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DDC232 Datasheet(PDF) 12 Page - Texas Instruments |
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DDC232 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 35 page ![]() Configuration Register Data Write Configuration Register Data Configuration Register Operations Test Pattern Read Configuration Register and Test Pattern RESET CLK_CFG DIN_CFG DCLK DOUT CONV Normal Operation t WTWR t WTRST MSB LSB MSB LSB t STCF t RST t HDCF DDC232 SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com NOTE: CLK must be running during Configuration Register write and read operations. Figure 8. Configuration Register Write and Read Operations Table 6. Timing for the Configuration Register Read/Write SYMBOL DESCRIPTION MIN TYP MAX UNITS tWTRST Wait Required from Reset High to First Rising Edge of CLK_CFG 2 ms Wait Required from Last CLK-CFG of Write Operation to tWTWR 2 ms First CLK_CFG of Read Operation tSTCF Set-Up Time from DIN_CFG to Falling Edge of CLK_CFG 10 ns tHDCF Hold Time for DIN_CFG After Falling Edge of CLK_CFG 10 ns tRST Pulse Width for RESET Active 1 ms 12 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 |
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