DDC232 datasheet(13/35 Pages) TI2

13 / 35 page

DDC232

www.ti.com

SBAS331D – AUGUST 2004 – REVISED APRIL 2010

Table 7. Configuration Register

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Range[2]

Range[1]

Range[0]

Format

Version

Clk_4x

Test

Bits 11–9

Range[2:0]. Full-scale range.

000: 12.5pC

100: 200pC

001: 50pC

101: 250pC

010: 100pC

110: 300pC

011: 150pC

111: 350pC (default)

Bit 8

Format. Data output format. This bit selects how many bits are used in the data output word.

0: 16-Bit Output

1: 20-Bit Output (default)

Bit 7

Version. Device version setting.

Must be set to '0' for DDC232C

Must be set to '1' for DDC232CK

Bit 6

Clk_4x. System clock divider. The Clk_4x input enables an internal divider on the system clock.

When Clk_4x = 1, the system clock is divided by 4. This allows a 4X faster system clock, which

in turn provides a finer quantization of the integration time because the CONV signal needs to be

synchronized with the system clock for the best performance.

0: Internal Clock Divider = 1 (default)

1: Internal Clock Divider = 4

Clk_4x BIT

CLK DIVIDER VALUE

CLK FREQUENCY

INTERNAL CLOCK FREQUENCY

5MHz

20MHz

5MHz

Bits 5–1

These bits must be set to '0'.

Bit 0

Test. Diagnostic test mode enable. When Test mode is used, the inputs (IN1 through IN32) are

disconnected from the DDC232 integrators to enable the user to measure a zero input signal

regardless of the current supplied to the inputs. Test mode works with both Continuous and

Noncontinuous modes.

0: Test Mode Off (default)

1: Test Mode On

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