DDC232 datasheet(20/35 Pages) TI2

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CLK

DVALID

PDCDV

PDDCDV

HDDODC

HDDODV

PDDCDO

Input32

MSB

Input

LSB

Input

MSB

Input5

LSB

Input4

MSB

Input2

LSB

Input1

MSB

Input1

LSB

Input32

MSB

DCLK

DOUT

DDC232

SBAS331D – AUGUST 2004 – REVISED APRIL 2010

www.ti.com

Table 12. Ideal Output Code(1) vs Input Signal

DATA FORMAT

INPUT

IDEAL OUTPUT CODE

The serial output data are provided in an offset binary

SIGNAL

FORMAT = 1

FORMAT = 0

code as shown in Table 12. The Format bit in the

≥ 100% FS

1111 1111 1111 1111 1111

1111 1111 1111 1111

configuration register selects how many bits are used

0.001531% FS

0000 0001 0000 0001 0000

0000 0001 0000 0001

in the output word. When Format = 1, 20 bits are

0.001436% FS

0000 0001 0000 0000 1111

0000 0001 0000 0000

used. When Format = 0, the lower 4 bits are

0.000191% FS

0000 0001 0000 0000 0010

0000 0001 0000 0000

truncated so that only 16 bits are used. Note that the

LSB size is 16 times bigger when Format = 0. An

0.000096% FS

0000 0001 0000 0000 0001

0000 0001 0000 0000

offset is included in the output to allow slightly

0% FS

0000 0001 0000 0000 0000

0000 0001 0000 0000

negative inputs (for example, from board leakages)

–0.3955% FS

0000 0000 0000 0000 0000

0000 0000 0000 0000

from clipping the reading. This offset is approximately

0.4% of the positive full-scale.

(1)

Excludes the effects of noise, INL, offset, and gain errors.

BLANKSPACE

DATA RETRIEVAL

Make sure not to retrieve data around changes in

In both the Continuous and Noncontinuous modes of

CONV because this can introduce noise. Stop activity

operation, the data from the last conversion are

on DCLK at least 10ms before or after a CONV

available for retrieval on the falling edge of DVALID

transition.

(see Figure 17 and Table 13). Data are shifted out on

Setting the Format bit = 0 (16-bit output word) will

the falling edge of the data clock, DCLK.

reduce the time needed to retrieve data by 20% since

there are fewer bits to shift out. This can be useful in

multichannel systems requiring only 16 bits of

resolution.

Figure 17. Digital Interface Timing for Data Retrieval From a Single DDC232

Table 13. Timing for DDC232 Data Retrieval

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tPDCDV

Propagation Delay from Falling Edge of CLK to DVALID Low

tPDDCDV

Propagation Delay from Falling Edge of DCLK to DVALID High

tHDDODV

Hold Time that DOUT is Valid Before the Falling Edge of DVALID

400

tHDDODC

Hold Time that DOUT is Valid After Falling Edge of DCLK

tPDDCDO

(1)

Propagation Delay from Falling Edge of DCLK to Valid DOUT

(1)

With a maximum load of one DDC232 (4pF typical) with an additional load of 5pF.

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