DS08MB200

SNLS197D – MAY 2006 – REVISED MARCH 2013

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PIN DESCRIPTIONS

Pin

WQFN Pin

I/O, Type

Description

Name

Number

SWITCH SIDE DIFFERENTIAL INPUTS

SIA_0+

30

I, LVDS

Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

SIA_0

−

29

LVPECL compatible.

SIA_1+

19

I, LVDS

Switch A-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

SIA_1

−

20

LVPECL compatible.

SIB_0+

28

I, LVDS

Switch B-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

SIB_0

−

27

LVPECL compatible.

SIB_1+

21

I, LVDS

Switch B-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

SIB_1

−

22

LVPECL compatible.

LINE SIDE DIFFERENTIAL INPUTS

LI_0+

40

I, LVDS

Line-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LI_0

−

39

LVPECL compatible.

LI_1+

9

I, LVDS

Line-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LI_1

−

10

LVPECL compatible.

SWITCH SIDE DIFFERENTIAL OUTPUTS

SOA_0+

34

O, LVDS

Switch A-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible(1)(2).

SOA_0

−

33

SOA_1+

15

O, LVDS

Switch A-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible(1)(2).

SOA_1

−

16

SOB_0+

32

O, LVDS

Switch B-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible(1)(2).

SOB_0

−

31

SOB_1+

17

O, LVDS

Switch B-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible(1)(2).

SOB_1

−

18

LINE SIDE DIFFERENTIAL OUTPUTS

LO_0+

42

O, LVDS

Line-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible(1)(2).

LO_0

−

41

LO_1+

7

O, LVDS

Line-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible(1)(2).

LO_1

−

8

DIGITAL CONTROL INTERFACE

MUX_S0

38

I, LVTTL

Mux Select Control Inputs (per channel) to select which Switch-side input, A or B, is passed through

MUX_S1

11

to the Line-side.

ENA_0

36

I, LVTTL

Output Enable Control for Switch A-side and B-side outputs. Each output driver on the A-side and B-

ENA_1

13

side has a separate enable pin.

ENB_0

35

ENB_1

14

ENL_0

45

I, LVTTL

Output Enable Control for The Line-side outputs. Each output driver on the Line-side has a separate

ENL_1

4

enable pin.

POWER

VDD

6, 12, 37,

I, Power

VDD = 3.3V ±0.3V.

43, 48

GND

2, 3, 46,

I, Power

Ground reference for LVDS and CMOS circuitry.

47(3)

For the WQFN package, the DAP is used as the primary GND connection to the device. The DAP is

the exposed metal contact at the bottom of the WQFN-48 package. It should be connected to the

ground plane with at least 4 vias for optimal AC and thermal performance.

N/C

1, 5, 23, 24,

No Connect

25, 26, 44

(1)

For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the APPLICATIONS section of this datasheet.

(2)

The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS08MB200 device have

been optimized for point-to-point backplane and cable applications.

(3)

Note that the DAP on the backside of the WQFN package is the primary GND connection for the device when using the WQFN

package.

2

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