DS08MB200

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SNLS197D – MAY 2006 – REVISED MARCH 2013

ELECTRICAL CHARACTERISTICS

Over recommended operating supply and temperature ranges unless other specified.

Symbol

Parameter

Conditions

Min

Typ(1)

Max

Units

LVTTL DC SPECIFICATIONS (MUX_Sn, ENA_n, ENB_n, ENL_n)

VIH

High Level Input Voltage

2.0

VDD

V

VIL

Low Level Input Voltage

GND

0.8

V

IIH

High Level Input Current

VIN = VDD = VDDMAX

−10

+10

µA

IIL

Low Level Input Current

VIN = VSS, VDD = VDDMAX

−10

+10

µA

CIN1

Input Capacitance

Any Digital Input Pin to VSS

3.5

pF

COUT1

Output Capacitance

Any Digital Output Pin to VSS

5.5

pF

VCL

Input Clamp Voltage

ICL = −18 mA

−1.5

−0.8

V

LVDS INPUT DC SPECIFICATIONS (SIA±, SIB±, LI±)

VTH

Differential Input High Threshold(2)

VCM = 0.8V or 1.2V or 3.55V,

0

100

mV

VDD = 3.6V

VTL

Differential Input Low Threshold(2)

VCM = 0.8V or 1.2V or 3.55V,

−100

0

mV

VDD = 3.6V

VID

Differential Input Voltage

VCM = 0.8V to 3.55V, VDD = 3.6V

100

2400

mV

VCMR

Common Mode Voltage Range

VID = 150 mV, VDD = 3.6V

0.05

3.55

V

CIN2

Input Capacitance

IN+ or IN

− to VSS

3.5

pF

IIN

Input Current

VIN = 3.6V, VDD = VDDMAX

−15

+15

µA

VIN = 0V, VDD = VDDMAX

−15

+15

µA

LVDS OUTPUT DC SPECIFICATIONS (SOA_n±, SOB_n±, LO_n±)

VOD

Differential Output Voltage(2)

RL is the internal 100Ω between OUT+

250

360

500

mV

and OUT

−

ΔVOD

Change in VOD between

-35

35

mV

Complementary States

VOS

Offset Voltage(3)

1.05

1.22

1.475

V

ΔVOS

Change in VOS between

-35

35

mV

Complementary States

IOS

Output Short Circuit Current

OUT+ or OUT

− Short to GND

−21

-40

mA

COUT2

Output Capacitance

OUT+ or OUT

− to GND when TRI-

5.5

pF

STATE

SUPPLY CURRENT (Static)

ICC

Supply Current

All inputs and outputs enabled and

active, terminated with differential load of

225

275

mA

100

Ω between OUT+ and OUT-.

ICCZ

Supply Current - Powerdown Mode

ENA_0 = ENB_0 = ENL_0= ENA_1 =

0.6

4.0

mA

ENB_1 = ENL_1 = L

SWITCHING CHARACTERISTICS—LVDS OUTPUTS

tLHT

Differential Low to High Transition

Use an alternating 1 and 0 pattern at 200

170

250

ps

Time

Mb/s, measure between 20% and 80% of

VOD.

(4)

tHLT

Differential High to Low Transition

170

250

ps

Time

tPLHD

Differential Low to High Propagation

Use an alternating 1 and 0 pattern at 200

1.0

2.5

ns

Delay

Mb/s, measure at 50% VOD between

input to output.

tPHLD

Differential High to Low Propagation

1.0

2.5

ns

Delay

tSKD1

Pulse Skew

|tPLHD–tPHLD|

(4)

25

75

ps

tSKCC

Output Channel to Channel Skew

Difference in propagation delay (tPLHD or

50

115

ps

tPHLD) among all output channels.

(4)

(1)

Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested.

(2)

Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−).

(3)

Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.

(4)

Not production tested. Ensured by statistical analysis on a sample basis at the time of characterization.

Copyright © 2006–2013, Texas Instruments Incorporated

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