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TLE5010 Datasheet(PDF) 29 Page - Infineon Technologies AG |
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TLE5010 Datasheet(HTML) 29 Page - Infineon Technologies AG |
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29 / 56 page ![]() TLE5010 Synchronous Serial Communication Interface (SSC) Draft Preliminary Data Sheet 29 V 0.9, 2007-05 The margin time in following table is the time between write access to the SSC Data Line and the earliest possible sample read of the TLE5010 itself for read back. It is useful to have a maximum distance between WRITE and subsequent READ. This ensures a reliable read back of the written data for the Slave-Active Byte generation. 8.2 SSC Baud rate The SSC Baud rate depends on the internal clock frequency. 12 internal digital clock cycles are necessary to ensure a reliable operation. Therefore the maximum SSC Baud rate depends on the external CLK. 8.3 SSC Spike Filter A SSC Spike Filter for all SSC lines can be selected via the SSC_FILT bit. 8.3.1 SSC Spike Filter Off When the spike filter is disabled, each slope of a rising voltage is used to define a bit. This is independent of the length of the sampled pulse. For example a positive spike generates therefore a rising and a falling edge. Table 14 Maximum Pull-up Time Margin with worst-case specified Timing SSC_FILT SSC_TIMING Min. tPU Margin 1) 1) Calculation: Margin=tSCKl(min)+tDATwMAX-(tPU)-tDATrMIN.For Margin<50 ns no problems can occur. Unit Comment 0 don’t care 90 ns 1 50 f SSC f CLK 2 ----------- = |
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