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TLE5010 Datasheet(PDF) 43 Page - Infineon Technologies AG |
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TLE5010 Datasheet(HTML) 43 Page - Infineon Technologies AG |
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43 / 56 page ![]() TLE5010 Data Communication via SSC Draft Preliminary Data Sheet 43 V 0.9, 2007-05 10.1 CRC Generation • This CRC is according to the J1850 Bus-Specification of 15.Feb.1994 for Class B Data Communication. • Every new transfer resets the CRC generation. • Every byte of a transfer will be taken into account to generate the CRC (also the sent command(s)). • Generator Polynom: X8+X4+X3+X2+1, for the CRC generation the fast CRC generation circuit is used. (See Figure 13) • The remainder of the fast CRC circuit is initial set to ’11111111B’. • Remainder is bit inverted before transmission. Figure 13 shows the fast CRC Polynom. The zero extension for initial CRC calculation is included! Figure 13 Fast CRC polynomial division circuit 10.2 Slave Active Byte Generation The position of the ’0’ in a nibble corresponds to the given slave number. The slave active byte (cccc_nnnn) is made up of a • low nibble (nnnn). One ’0’ is generated always according to the slave number. • high nibble (cccc). The ’0’ is only generated, if the readback CRC is correct. Slave1: S_NO = 0 bit 0 is pulled low Slave Active Byte: 1110_1110 Slave2: S_NO = 1 bit 1 is pulled low Slave Active Byte: 1101_1101 Slave3: S_NO = 2 bit 2 is pulled low Slave Active Byte: 1011_1011 Slace4: S_NO = 3 bit 3 is pulled low Slave Active Byte: 0111_0111 Example for a communication disturbed by other bus participants: Slave1: S_NO = 0 bit 0 is pulled low, but the high nibble remains as ’1111’. > Slave Active Byte: 1111_1110 X7 X6 X5 X4 X3 X2 X0 xor Input Serial CRC output TX_CRC X1 1 1 xor 1 xor 1 xor 1 1 1 1 & parallel Remainder |
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