F0448 datasheet(7/43 Pages) RENESAS

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F0448 Datasheet

X0008129 Rev.1.4

Feb 17, 2021

Page 7

Number

Name

Description

VCTRL0_A

1-bit DSA0 6dB attenuator control for channel A. Logic HIGH is for 6dB attenuated and logic LOW

is for 0dB attenuated.

DATA

Data input: 3.3V or 1.8V CMOS compatible.

CLK

Clock input: 3.3V or 1.8V CMOS compatible.

6, 21, 23, 25

VCC

Power Supply. Use bypass capacitors as close to pin as possible.

VCTRL0_B

1-bit DSA0 6dB attenuator control for channel B. Logic HIGH is for 6dB attenuated and logic LOW

is for 0dB attenuated.

RFIN_B

Input RF port for channel B that is internally matched to 50Ω. Must use external DC block.

10, 18, 20,

26, 28, 36

No internal connection. These pins can be left unconnected or be connected to ground

(recommended). Use a via as close to the pin as possible if grounded.

CSb_B

Chip Select bar input for channel B: 3.3V or 1.8V CMOS compatible. Logic LOW allows data to be

shifted in.

STBY_B

Standby pin for channel B (LOW/Open = device power ON, HIGH = device power OFF with SPI

still powered ON). An internal pull-

down resistor of 57kΩ connects between this pin and GND.

VCTRL1_B

Bit 0 for DSA2 channel B attenuator. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB

attenuated.

VCTRL2_B

Bit 1 for DSA2 channel B attenuator. Logic HIGH is for 12dB attenuated and logic LOW is for 0dB

attenuated.

RFOUT_B

Output RF port for channel B. Use external DC block as close to the pin as possible.

RDSET

Connect external resistor to GND to optimize amplifier bias. Used with pin 24.

RSET

Connect external resistor to GND to optimize amplifier bias. Used with pin 22.

RFOUT_A

Output RF port for channel A. Use external DC block as close to the pin as possible.

VCTRL2_A

Bit 1 for DSA2 channel A attenuator. Logic HIGH is for 12dB attenuated and logic LOW is for 0dB

attenuated.

VCTRL1_A

Bit 0 for DSA2 channel A attenuator. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB

attenuated.

STBY_A

Standby pin for channel A (LOW/Open = device power ON, HIGH = device power OFF with SPI

still powered ON). An internal pull-

down resistor of 57kΩ connects between this pin and GND.

CSb_A

Chip Select bar input for channel A: 3.3V or 1.8V CMOS compatible. Logic LOW allows data to be

shifted in.

— EPAD

Exposed paddle. Internally connected to ground. Solder this exposed paddle to a printed circuit

board (PCB) pad that uses multiple ground vias to provide heat transfer out of the device into the

PCB ground planes. These multiple ground vias are also required to achieve the specified RF

performance.

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