F0448 datasheet(10/43 Pages) RENESAS

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F0448 Datasheet

X0008129 Rev.1.4

Feb 17, 2021

Page 10

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

DSA0 Phase Settling Time

tDSA0_1_PH

50% CTRL to within 1 degree of

final value, 0dB state to 6dB

state

tDSA0_2_PH

50% CTRL to within 1 degree of

final value, 6dB state to 0dB

state

DSA2 Phase Settling Time

tDSA2_1_PH

50% CTRL to within 1 degree of

final value, 0dB state to 18dB

state

tDSA0_1_PH

50% CTRL to within 1 degree of

final value, 18dB state to 0dB

state

Stability K factor

KFACT

Over entire temperature range

1.4

unit

Serial Clock Speed

SPICLK

MHz

CSb_A, CSb_B to first serial

clock rising edge

tLS

SPI 3 wire bus. 50% of CSb

falling edge to 50% of CLK rising

edge.

Serial Data Hold Time

SPI 3 wire bus. 50% of CLK

rising edge to 50% of Data falling

edge.

Final serial clock rising edge to

CSb

tLC

SPI 3 wire bus. 50% of CLK

rising edge to 50% of CSb rising

edge.

RF Input Return Loss

RLIN

RF Output Return Loss

RLOUT

Gain

GMAX

13.5

GMIN

Maximum attenuation

-38.1

-32

-26.4

GTEMP

Variation over temperature

±0.15

GVAR

Variation over frequency [3]

±0.2

DSA0 Absolute Accuracy

INLDSA0

0.52

DSA1 Step Error

DNLDSA1

0.16

DSA1 Absolute Accuracy

INLDSA1

0.55

DSA2 Step Error

DNLDSA2

0.32

DSA2 Absolute Accuracy

INLDSA2

0.43

Relative Phase DSA0

PH_DSA0

6.6

deg

Phase Deviation DSA1

PH_DSA1

Between adjacent states

deg

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