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AFE5804 Datasheet(PDF) 44 Page - Texas Instruments |
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AFE5804 Datasheet(HTML) 44 Page - Texas Instruments |
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44 / 63 page ![]() FCLKP LCLKP OUTP PHASE_DDR<1:0>= '00' PHASE_DDR<1:0>= '01' PHASE_DDR<1:0>= '10' PHASE_DDR<1:0>= '11' FCLKP LCLKP OUTP FCLKP LCLKP OUTP FCLKP LCLKP OUTP FCLKP LCLKP OUTP AFE5804 SBOS442C – JUNE 2008 – REVISED OCTOBER 2011 www.ti.com BIT CLOCK PROGRAMMABILITY The output interface of the AFE5804 is normally a DDR interface, with the LCLK rising edge and falling edge transitions in the middle of alternate data windows. Figure 94 shows this default phase. Figure 94. LCLK Default Phase The phase of LCLK can be programmed relative to the output frame clock and data using bits PHASE_DDR <1:0>. Figure 95 shows the LCLK phase modes. Figure 95. LCLK Phase Programmability Modes 44 Copyright © 2008–2011, Texas Instruments Incorporated |
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