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SMBP2501BPB Datasheet(PDF) 65 Page - SONiX Technology Company |
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SMBP2501BPB Datasheet(HTML) 65 Page - SONiX Technology Company |
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65 / 107 page  SN8P2501B 8-Bit Micro-Controller SONiX TECHNOLOGY CO., LTD Page 65 Version 2.1 6.6 INT0 (P0.0) INTERRUPT OPERATION When the INT0 trigger occurs, the P00IRQ will be set to “1” no matter the P00IEN is enable or disable. If the P00IEN = 1 and the trigger event P00IRQ is also set to be “1”. As the result, the system will execute the interrupt vector (ORG 8). If the P00IEN = 0 and the trigger event P00IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even when the P00IRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation. Note: The interrupt trigger direction of P0.0 is control by PEDGE register. 0BFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEDGE - - - P00G1 P00G0 - - - Read/Write - - - R/W R/W - - - After reset - - - 1 0 - - - Bit[4:3] P00G[1:0]: P0.0 interrupt trigger edge control bits. 00 = reserved. 01 = rising edge. 10 = falling edge. 11 = rising/falling bi-direction (Level change trigger). Example: Setup INT0 interrupt request and bi-direction edge trigger. MOV A, #18H B0MOV PEDGE, A ; Set INT0 interrupt trigger as bi-direction edge. B0BSET FP00IEN ; Enable INT0 interrupt service B0BCLR FP00IRQ ; Clear INT0 interrupt request flag B0BSET FGIE ; Enable GIE Example: INT0 interrupt service routine. ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE: … ; Push routine to save ACC and PFLAG to buffers. B0BTS1 FP00IRQ ; Check P00IRQ JMP EXIT_INT ; P00IRQ = 0, exit interrupt vector B0BCLR FP00IRQ ; Reset P00IRQ … ; INT0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector |
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