SMBP2501BPB datasheet(69/107 Pages) SONIX

69 / 107 page

SN8P2501B

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 69

Version 2.1

6.9 MULTI-INTERRUPT OPERATION

Under certain condition, the software designer uses more than one interrupt requests. Processing multi-interrupt

request requires setting the priority of the interrupt requests. The IRQ flags of interrupts are controlled by the interrupt

event. Nevertheless, the IRQ flag

“1” doesn’t mean the system will execute the interrupt vector. In addition, which

means the IRQ flags can be set

“1” by the events without enable the interrupt. Once the event occurs, the IRQ will be

logic

“1”. The IRQ and its trigger event relationship is as the below table.

Interrupt Name

Trigger Event Description

P00IRQ

P0.0 trigger controlled by PEDGE

T0IRQ

T0C overflow

TC0IRQ

TC0C overflow

For multi-interrupt conditions, two things need to be taking care of. One is to set the priority for these interrupt requests.

Two is using IEN and IRQ flags to decide which interrupt to be executed. Users have to check interrupt control bit and

interrupt request flag in interrupt routine.



Example: Check the interrupt request under multi-interrupt operation

ORG

; Interrupt vector

JMP

INT_SERVICE

INT_SERVICE:

…

; Push routine to save ACC and PFLAG to buffers.

INTP00CHK:

; Check INT0 interrupt request

B0BTS1

FP00IEN

; Check P00IEN

JMP

INTT0CHK

; Jump check to next interrupt

B0BTS0

FP00IRQ

; Check P00IRQ

JMP

INTP00

; Jump to INT0 interrupt service routine

INTT0CHK:

; Check T0 interrupt request

B0BTS1

FT0IEN

; Check T0IEN

JMP

INTTC0CHK

; Jump check to next interrupt

B0BTS0

FT0IRQ

; Check T0IRQ

JMP

INTT0

; Jump to T0 interrupt service routine

INTTC0CHK:

; Check TC0 interrupt request

B0BTS1

FTC0IEN

; Check TC0IEN

JMP

INT_EXIT

; Jump to exit of IRQ

B0BTS0

FTC0IRQ

; Check TC0IRQ

JMP

INTTC0

; Jump to TC0 interrupt service routine

INT_EXIT:

…

; Pop routine to load ACC and PFLAG from buffers.

RETI

; Exit interrupt vector

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