SMBP2501BPB datasheet(68/107 Pages) SONIX

68 / 107 page

SN8P2501B

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 68

Version 2.1

6.8 TC0 INTERRUPT OPERATION

When the TC0C counter overflo

ws, the TC0IRQ will be set to “1” no matter the TC0IEN is enable or disable. If the

TC0IEN and the trigger event TC0IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the

TC0IEN = 0, the trigger event TC0IRQ is still set

to be “1”. Moreover, the system won’t execute interrupt vector even

when the TC0IRQ

is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.



Example: TC0 interrupt request setup.

B0BCLR

FTC0IEN

; Disable TC0 interrupt service

B0BCLR

FTC0ENB

; Disable TC0 timer

MOV

A, #20H

;

B0MOV

TC0M, A

; Set TC0 clock = Fcpu / 64

MOV

A, #74H

; Set TC0C initial value = 74H

B0MOV

TC0C, A

; Set TC0 interval = 10 ms

B0BSET

FTC0IEN

; Enable TC0 interrupt service

B0BCLR

FTC0IRQ

; Clear TC0 interrupt request flag

B0BSET

FTC0ENB

; Enable TC0 timer

B0BSET

FGIE

; Enable GIE



Example: TC0 interrupt service routine.

ORG

; Interrupt vector

JMP

INT_SERVICE

INT_SERVICE:

…

; Push routine to save ACC and PFLAG to buffers.

B0BTS1

FTC0IRQ

; Check TC0IRQ

JMP

EXIT_INT

; TC0IRQ = 0, exit interrupt vector

B0BCLR

FTC0IRQ

; Reset TC0IRQ

MOV

A, #74H

B0MOV

TC0C, A

; Reset TC0C.

…

; TC0 interrupt service routine

…

EXIT_INT:

…

; Pop routine to load ACC and PFLAG from buffers.

RETI

; Exit interrupt vector

SMBP2501BPB Datasheet(PDF) 68 Page - SONiX Technology Company

SMBP2501BPB Datasheet(HTML) 68 Page - SONiX Technology Company

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL