tD

VCC

VCCmin

VOH

VOL

VIT+

VIT-

RESET

VCC(0v)

tD

tP_HL

VHYS

10

LP3470A

SNVSBF5C – JULY 2019 – REVISED MAY 2020

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Feature Description (continued)

The recommended maximum delay capacitor for the LP3470A is limited to 10 µF as this ensures there is enough

time for the capacitor to fully discharge when the reset condition occurs. When a voltage fault occurs, the

previously charged up capacitor discharges, and if the monitored voltage returns from the fault condition before

the delay capacitor discharges completely, the delay capacitor will begin charging from a voltage above zero and

the reset delay will be shorter than expected. Larger delay capacitors can be used so long as the capacitor has

enough time to fully discharge during the duration of the voltage fault.

8.3.2 RESET Output

In applications like microprocessor (µP) systems, errors might occur in system operation during power up, power

down, or brownout conditions. It is imperative to monitor the power supply voltage to prevent these errors from

occurring.

The LP3470A asserts a reset signal whenever the VCC supply voltage is below a threshold (VIT-) voltage.

RESET is ensured to be a logic low for VCC > 0.95 V. Once VCC exceeds the reset threshold plus a hysteresis

voltage, the reset is kept asserted for a time period (tD) programmed by an external capacitor (CSRT); after this

interval RESET goes to logic high. If a brownout condition occurs (monitored voltage falls below the reset

threshold), RESET goes low. When VCC returns above the reset threshold plus a hysteresis voltage, RESET

remains low for a time period tD before going to logic high. Figure 9 shows this behavior.

Figure 9. RESET Output Timing Diagram

8.3.3 Pull-up Resistor Selection

The RESET output structure of the LP3470A is an open-drain N-channel MOSFET switch. A pull-up resistor

(Rpull-up) must be connected to VCC to keep the output logic high when RESET is not asserted.

Connect the pull-up resistor to the desired pull-up voltage source and RESET can be pulled up to any voltage up

to 10 V independent of the VCC voltage. To ensure proper voltage levels, give some consideration when

choosing the pull-up resistor values. Rpull-up must be large enough to limit the current through the output within

the recommended operating conditions. The pull-up resistor value determines the actual VOL, the output

capacitive loading, and the output leakage current (ILKG(OD)). A typical pull-up resistor value of 20 kΩ is sufficient

in most applications.

8.3.4 VCC Transient Immunity

The LP3470A is immune to quick voltage transients or excursions on VCC. Sensitivity to transients depends on

both pulse duration and overdrive. Overdrive is defined by how much VCC deviates from the specified threshold.

Threshold overdrive is calculated as a percent of the threshold in question, as shown in Equation 6. A 0.1-µF

bypass capacitor mounted close to VCC provides additional transient immunity.

Overdrive = | (VCC / VIT- – 1) × 100% |

(6)