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MF5438AMEP Datasheet(PDF) 39 Page - Texas Instruments

Part # MF5438AMEP
Description  MIXED SIGNAL MICROCONTROLLER
PDF  100 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

MF5438AMEP Datasheet(HTML) 39 Page - Texas Instruments

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MSP430F5438A-EP
www.ti.com
SLAS967A – JANUARY 2014 – REVISED JANUARY 2014
Thermal Information
MSP430F5438A-EP
THERMAL METRIC(1)
GQW
PZ
UNITS
113 PINS
100 PINS
θJA
Junction-to-ambient thermal resistance(2)
43.6
49
θJCtop
Junction-to-case (top) thermal resistance(3)
16.6
9.3
θJB
Junction-to-board thermal resistance(4)
17.8
25
°C/W
ψJT
Junction-to-top characterization parameter(5)
0.3
0.2
ψJB
Junction-to-board characterization parameter(6)
15.1
24.7
θJCbot
Junction-to-case (bottom) thermal resistance(7)
N/A
N/A
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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