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MF5438AMEP Datasheet(PDF) 9 Page - Texas Instruments |
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MF5438AMEP Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 100 page ![]() MSP430F5438A-EP www.ti.com SLAS967A – JANUARY 2014 – REVISED JANUARY 2014 Table 2. Terminal Functions (continued) TERMINAL NO. I/O(1) DESCRIPTION NAME GQW PZ General-purpose digital I/O Clock signal input – USCI_B2 SPI slave mode P9.3/UCB2CLK/UCA2STE E9 71 I/O Clock signal output – USCI_B2 SPI master mode Slave transmit enable – USCI_A2 SPI mode General-purpose digital I/O P9.4/UCA2TXD/UCA2SIMO C11 72 I/O Transmit data – USCI_A2 UART mode Slave in, master out – USCI_A2 SPI mode General-purpose digital I/O P9.5/UCA2RXD/UCA2SOMI B12 73 I/O Receive data – USCI_A2 UART mode Slave out, master in – USCI_A2 SPI mode P9.6 B11 74 I/O General-purpose digital I/O P9.7 A12 75 I/O General-purpose digital I/O General-purpose digital I/O Slave transmit enable – USCI_B3 SPI mode P10.0/UCB3STE/UCA3CLK D9 76 I/O Clock signal input – USCI_A3 SPI slave mode Clock signal output – USCI_A3 SPI master mode General-purpose digital I/O P10.1/UCB3SIMO/UCB3SDA A11 77 I/O Slave in, master out – USCI_B3 SPI mode I2C data – USCI_B3 I2C mode General-purpose digital I/O P10.2/UCB3SOMI/UCB3SCL D8 78 I/O Slave out, master in – USCI_B3 SPI mode I2C clock – USCI_B3 I2C mode General-purpose digital I/O Clock signal input – USCI_B3 SPI slave mode P10.3/UCB3CLK/UCA3STE B10 79 I/O Clock signal output – USCI_B3 SPI master mode Slave transmit enable – USCI_A3 SPI mode General-purpose digital I/O P10.4/UCA3TXD/UCA3SIMO A10 80 I/O Transmit data – USCI_A3 UART mode Slave in, master out – USCI_A3 SPI mode General-purpose digital I/O P10.5/UCA3RXD/UCA3SOMI B9 81 I/O Receive data – USCI_A3 UART mode Slave out, master in – USCI_A3 SPI mode P10.6 A9 82 I/O General-purpose digital I/O P10.7 B8 83 I/O General-purpose digital I/O General-purpose digital I/O P11.0/ACLK A8 84 I/O ACLK output (divided by 1, 2, 4, 8, 16, or 32) General-purpose digital I/O P11.1/MCLK D7 85 I/O MCLK output General-purpose digital I/O P11.2/SMCLK A7 86 I/O SMCLK output DVCC4 B7 87 Digital power supply DVSS4 B6 88 Digital ground supply General-purpose digital I/O P5.2/XT2IN A6 89 I/O Input terminal for crystal oscillator XT2 General-purpose digital I/O P5.3/XT2OUT A5 90 I/O Output terminal of crystal oscillator XT2 Test mode pin – Selects four wire JTAG operation. TEST/SBWTCK(3) D6 91 I Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated General-purpose digital I/O PJ.0/TDO(4) B5 92 I/O JTAG test data output port General-purpose digital I/O PJ.1/TDI/TCLK(4) A4 93 I/O JTAG test data input or test clock input (3) See Bootstrap Loader (BSL) and JTAG Operation for use with BSL and JTAG functions, respectively. (4) See JTAG Operation for use with JTAG function. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 9 |
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