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Capacitive Loads

OPA698

C

L

R

L

R

T

R

S

R

G

R

F

V

O

R

L is optional

S0048-01

Frequency Response Compensation

Pulse Settling Time

Distortion

OPA698M

SGLS287A – MAY 2005 – REVISED MARCH 2006

Capacitive loads, such as the input to ADCs, decreases the amplifier phase margin, which may cause

high-frequency peaking or oscillations. Capacitive loads

≥2 pF should be isolated by connecting a small resistor

in series with the output, as shown in Figure 68. Increasing the gain from +2 improves the capacitive drive

capabilities due to increased phase margin.

Figure 68. Driving Capacitive Loads

In general, capacitive loads should be minimized for optimum high-frequency performance. The capacitance of

coax cable (29 pF/ft for RG-58) will not load the amplifier when the coaxial cable, or transmission line, is

terminated in its characteristic impedance.

The OPA698 is internally compensated to be unity-gain stable, and has a nominal phase margin of 60° at a gain

of +2. Phase margin and peaking improve at higher gains. Recall that an inverting gain of –1 is equivalent to a

gain of +2 for bandwidth purposes (that is, noise gain = 2). Standard external compensation techniques work with

this device. For example, in the inverting configuration, the bandwidth may be limited without modifying the

inverting gain by placing a series RC network to ground on the inverting node. This has the effect of increasing

the noise gain at high frequencies, which limits the bandwidth.

To maintain a wide bandwidth at high gains, cascade several op amps, or use the high-gain optimized OPA699.

In applications where a large feedback resistor is required, such as photodiode transimpedance amplifier, the

parasitic capacitance from the inverting input to ground causes peaking or oscillations. To compensate for this

effect, connect a small capacitor in parallel with the feedback resistor. The bandwidth will be limited by the pole

that the feedback resistor and this capacitor create. In other high-gain applications, use a three resistor Tee

network to reduce the RC time constants set by the parasitic capacitances. Be careful not to increase the noise

generated by this feedback network too much.

The OPA698 is capable of an extremely fast settling time in response to a pulse input. Frequency response

flatness and phase linearity are needed to obtain the best settling times. For capacitive loads, such as an ADC,

use the recommended RS in the typical performance curve RS vs Capacitive Load. Extremely fine-scale settling

(0.01%) requires close attention to ground return current in the supply decoupling capacitors.

The pulse settling characteristics, when recovering from overdrive, are good.

The OPA698 distortion performance is specified for a 500-

Ω load, such as an ADC. Driving loads with smaller

resistance increases the distortion, as illustrated in Figure 69. Remember to include the feedback network in the

load resistance calculations.

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