DA9313 datasheet(33/55 Pages) RENESAS

33 / 55 page

DA9313

High Efficiency Dual Cell Switched Capacitor Divider

Datasheet

Revision 3.6

16-Jun-2023

CFR0011-120-00

33 of 55

When the warning comparator triggers, the status bit VBAT_WARN is asserted and the event

E_VBAT_WARN is generated. If not masked via M_VBAT_WARN, the output port nIRQ is asserted

(providing a GPIO is configured as nIRQ). The host processor is then informed that the input voltage

level is close to critical and it can take action such as powering down the application.

If the input voltage keeps dropping and the shutdown comparator is triggered the PVC is disabled

and the VBAT_UV_CRIT bit is asserted in FAULT_LOG. When the VBAT voltage recovers over

VTH_UVLO_VDD + VHYST_UVLO_VDD, DA9313 enters ACTIVE mode after having performed an OTP read.

11.5.2

Over-Temperature

FAULT RECOVERY mode is entered when TJ

≥ TTH_CRIT and is exited when TJ < TTH_CRIT. The

TEMP_CRIT bit is asserted in FAULT_LOG.

11.5.3

PVC Current Limit

When the PVC hits the current limit, FAULT RECOVERY mode is entered and is immediately exited,

because the root cause (current limit reached) is removed when the PVC is disabled. The

PVC_OC_CRIT bit is asserted in FAULT_LOG.

11.5.4

PVC Start-Up Failure

FAULT RECOVERY mode is entered when the PVC has failed its start-up procedure. This occurs

when the output voltage has not reached a voltage close to VDD/2 within approximately 20 ms.

FAULT RECOVERY mode is immediately exited and a new power up is started. The PVC_RAMPUP

bit is asserted in FAULT_LOG.

11.6 VCORE Voltage Regulator

The VCORE supply is a 4 V rail internally generated by DA9313 for the internal analog and digital

supply. It is always enabled except in OFF mode.

The additional VDDIO rail is internally generated directly from VCORE. The slave has VDDIO

disabled.

VCORE is the only regulator with an external bypass capacitor and can supply up to 20 mA to an

external circuit.

11.7 VDDIO Generation

The VDDIO rail is internally generated by DA9313 from VCORE and is assigned to the I/O interfaces

and to the GPIOs. The VDDIO is controlled via VDDIO_EN bit. The rail assignment determines the

IO voltage levels and logical thresholds see section 7.5. A specific VDDIO voltage can be selected

via VDDIO_CONF (1.5 V, 1.8 V, 2.8 V, or 3.3 V).

The VDDIO generation is off in OFF and POWER_DOWN modes, and always in the slave device. In

SLEEP mode the VDDIO generation is disabled if VDDIO_SL is asserted.

The internally generated VDDIO is monitored for under voltage VTH_UVLO_IO. If VDDIO voltage is

not in range, the I2C interface is reset. All IOs are run from VCORE if VDDIO is disabled. All IOs are

supplied on VCORE only when in master/slave mode (it is not possible to enable VDDIO in these

modes).

DA9313 Datasheet(PDF) 33 Page - Renesas Technology Corp

DA9313 Datasheet(HTML) 33 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Datasheet Download

Link URL